forked from Apple-2-HW/fpga-disk-controller
45 lines
936 B
Verilog
45 lines
936 B
Verilog
//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.9.0.99.2
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`timescale 1 ns / 1 ps
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module tb;
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reg [11:0] Address = 12'b0;
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reg OutClock = 0;
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reg OutClockEn = 0;
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reg Reset = 0;
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wire [7:0] Q;
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integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0;
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GSR GSR_INST (.GSR(1'b1));
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PUR PUR_INST (.PUR(1'b1));
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codeROM u1 (.Address(Address), .OutClock(OutClock), .OutClockEn(OutClockEn),
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.Reset(Reset), .Q(Q)
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);
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initial
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begin
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Address <= 0;
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#100;
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@(Reset == 1'b0);
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for (i1 = 0; i1 < 4099; i1 = i1 + 1) begin
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@(posedge OutClock);
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#1 Address <= Address + 1'b1;
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end
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end
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always
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#5.00 OutClock <= ~ OutClock;
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initial
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begin
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OutClockEn <= 1'b0;
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#100;
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@(Reset == 1'b0);
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OutClockEn <= 1'b1;
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end
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initial
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begin
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Reset <= 1'b1;
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#100;
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Reset <= 1'b0;
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end
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endmodule |