forked from Apple-2-HW/fpga-disk-controller
113 lines
3.6 KiB
Verilog
113 lines
3.6 KiB
Verilog
`timescale 1 ns / 1 ps
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module top(
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// bus interface
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input [11:0] addr,
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input fclk, // Clock for serial communication, either 7 or 8 MHz (7 MHz on Apple II)
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input q3, // 2 MHz non-symmetric timing signal
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inout [7:0] data,
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input rw, // 1 means read, 0 means write
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input _iostrobe, // goes low during read or write to any address $C800-$CFFF
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input _iosel, // goes low during read or write to $CX00-$CXFF, where X is slot number
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input _devsel, // goes low during read or write to $C0(X+8)0-$C0(X+8)F, where X is slot number. IWM: Falling edge latches A3-A0. Rising edge of (Q3 or _devsel) qualifies write register data
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input _reset,
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// disk interface
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output wrdata,
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output [3:0] phase,
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output _wrreq,
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output _enbl1,
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inout _enbl2, // output that may be hardwired to ground when connected to a drive
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inout select, // output that may be hardwired to ground when connected to a drive
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inout _en35, // output that may be hardwired to ground when connected to a drive
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input sense,
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input rddata,
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// SPI
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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output spi_cs,
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// level-shifting buffers
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output _en245, // bidirectional connection of data bus to FPGA
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// debugging: LEDs or switches or misc stuff
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output [7:0] debugInfo
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);
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wire isOutputting;
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wire romExpansionActive; // 1 if the Yellowstone card's ROM is the currently selected slot ROM
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assign debugInfo = { romExpansionActive, rw, q3, isOutputting/*_devsel*/, _iosel, _iostrobe, _reset, spi_miso }; //{ romActive, 6'b000000, spi_miso };
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wire _romoe;
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//reg [1:0] en245Delay;
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//always @(posedge fclk) begin
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// en245Delay <= { en245Delay[0], (~_devsel || ~_romoe) };
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//end
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assign _en245 = ~(/*~q3 &&*//*(en245Delay == 2'b11) &&*/ (~_devsel || ~_romoe)); // IWM selected or ROM outputting
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// IMPORTANT! TO-DO
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// for select, _enbl2, _en35, these outputs may be driven externally to ground!
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// never drive these actively high. configure as inout, enable the internal pull-up, and set output value to 0 or hi-Z
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// may need to pause a few microseconds after setting these to hi-Z to let the pull-up work. It's around 50Kohm equivalent.
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// RC time constant assuming 10 pF trace capacitance is 0.5 microseconds
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wire _enbl2_from_iwm;
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assign _enbl2 = 1'bZ;
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assign select = 1'bZ;
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assign _en35 = 1'bZ;
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addrDecoder myAddrDecoder(
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.addr(addr),
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.fclk(fclk),
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._iostrobe(_iostrobe),
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._iosel(_iosel),
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._reset(_reset),
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._romoe(_romoe),
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.romExpansionActive(romExpansionActive)
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);
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wire [7:0] iwmDataOut;
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iwm myIwm(
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.addr(addr[3:0]),
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._devsel(_devsel),
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.fclk(fclk),
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.q3(q3),
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._reset(_reset),
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.dataIn(data),
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.dataOut(iwmDataOut),
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.wrdata(wrdata),
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.phase(phase),
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._wrreq(_wrreq),
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._enbl1(_enbl1),
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._enbl2(_enbl2_from_iwm),
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.sense(sense),
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.rddata(rddata)
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);
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wire [7:0] romOutput;
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codeROM myROM(
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.Address(addr[11:0]),
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.OutClock(fclk), // use internal clock?
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.OutClockEn(1'b1),
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.Reset(1'b0),
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.Q(romOutput)
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);
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//reg [1:0] lastDataEnable;
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//always @(posedge fclk) begin
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// lastDataEnable <= { lastDataEnable[0], (rw == 1 && _romoe == 0) || (rw == 1 && _devsel == 0 && addr[0] == 0) };
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//end
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// provide data from the card's ROM, or the IWM?
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// IWM registers are read during any operation in which A0 is 0
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assign isOutputting = (rw && ~_romoe) /*|| (rw == 1 && _devsel == 0 && addr[0] == 0)*/;
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assign data = (/*lastDataEnable == 2'b11 &&*/ rw == 1 && _romoe == 0) ? romOutput :
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(/*lastDataEnable == 2'b11 &&*/ rw == 1 && _devsel == 0 && addr[0] == 0) ? iwmDataOut :
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8'bZZZZZZZZ;
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endmodule
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