forked from Apple-2-HW/fpga-disk-controller
1164 lines
47 KiB
Plaintext
1164 lines
47 KiB
Plaintext
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Loading design for application trce from file liron_fpgatop.ncd.
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Design name: top
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-1200HC
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Package: TQFP100
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Performance: 4
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Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga.
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Package Status: Final Version 1.42.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.9.0.99.2
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Thu Feb 22 10:56:44 2018
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf
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Design file: liron_fpgatop.ncd
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Preference file: liron_fpgatop.prf
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Device,speed: LCMXO2-1200HC,4
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Report level: verbose report, limited to 10 items per preference
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--------------------------------------------------------------------------------
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Report Type: based on TRACE automatically generated preferences
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
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565 items scored, 124 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 2.923ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i2 (to fclk_c +)
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FF myIwm/shifter_i0_i1
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Delay: 9.308ns (26.1% logic, 73.9% route), 5 logic levels.
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Constraint Details:
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9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_19:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.520 R8C15C.Q0 to R9C14D.A0 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14D.A0 to R9C14D.F0 myIwm/SLICE_37
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ROUTE 1 1.535 R9C14D.F0 to R9C14D.B1 myIwm/n4
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CTOF_DEL --- 0.495 R9C14D.B1 to R9C14D.F1 myIwm/SLICE_37
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ROUTE 3 1.749 R9C14D.F1 to R8C13C.B0 myIwm/n87
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CTOF_DEL --- 0.495 R8C13C.B0 to R8C13C.F0 myIwm/SLICE_41
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ROUTE 1 0.967 R8C13C.F0 to R8C13B.A1 myIwm/n9
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CTOF_DEL --- 0.495 R8C13B.A1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.105 R8C13B.F1 to R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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9.308 (26.1% logic, 73.9% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_19:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R10C13A.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.923ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i6 (to fclk_c +)
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FF myIwm/shifter_i0_i5
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Delay: 9.308ns (26.1% logic, 73.9% route), 5 logic levels.
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Constraint Details:
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9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.520 R8C15C.Q0 to R9C14D.A0 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14D.A0 to R9C14D.F0 myIwm/SLICE_37
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ROUTE 1 1.535 R9C14D.F0 to R9C14D.B1 myIwm/n4
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CTOF_DEL --- 0.495 R9C14D.B1 to R9C14D.F1 myIwm/SLICE_37
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ROUTE 3 1.749 R9C14D.F1 to R8C13C.B0 myIwm/n87
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CTOF_DEL --- 0.495 R8C13C.B0 to R8C13C.F0 myIwm/SLICE_41
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ROUTE 1 0.967 R8C13C.F0 to R8C13B.A1 myIwm/n9
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CTOF_DEL --- 0.495 R8C13B.A1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.105 R8C13B.F1 to R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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9.308 (26.1% logic, 73.9% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R10C13D.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.923ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i4 (to fclk_c +)
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FF myIwm/shifter_i0_i3
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Delay: 9.308ns (26.1% logic, 73.9% route), 5 logic levels.
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Constraint Details:
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9.308ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.923ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_20:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.520 R8C15C.Q0 to R9C14D.A0 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14D.A0 to R9C14D.F0 myIwm/SLICE_37
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ROUTE 1 1.535 R9C14D.F0 to R9C14D.B1 myIwm/n4
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CTOF_DEL --- 0.495 R9C14D.B1 to R9C14D.F1 myIwm/SLICE_37
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ROUTE 3 1.749 R9C14D.F1 to R8C13C.B0 myIwm/n87
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CTOF_DEL --- 0.495 R8C13C.B0 to R8C13C.F0 myIwm/SLICE_41
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ROUTE 1 0.967 R8C13C.F0 to R8C13B.A1 myIwm/n9
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CTOF_DEL --- 0.495 R8C13B.A1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.105 R8C13B.F1 to R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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9.308 (26.1% logic, 73.9% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_20:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R10C13B.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.909ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i0 (to fclk_c +)
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Delay: 9.294ns (26.2% logic, 73.8% route), 5 logic levels.
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Constraint Details:
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9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_18:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.520 R8C15C.Q0 to R9C14D.A0 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14D.A0 to R9C14D.F0 myIwm/SLICE_37
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ROUTE 1 1.535 R9C14D.F0 to R9C14D.B1 myIwm/n4
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CTOF_DEL --- 0.495 R9C14D.B1 to R9C14D.F1 myIwm/SLICE_37
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ROUTE 3 1.749 R9C14D.F1 to R8C13C.B0 myIwm/n87
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CTOF_DEL --- 0.495 R8C13C.B0 to R8C13C.F0 myIwm/SLICE_41
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ROUTE 1 0.967 R8C13C.F0 to R8C13B.A1 myIwm/n9
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CTOF_DEL --- 0.495 R8C13B.A1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.091 R8C13B.F1 to R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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9.294 (26.2% logic, 73.8% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_18:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R9C13A.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.909ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i7 (to fclk_c +)
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Delay: 9.294ns (26.2% logic, 73.8% route), 5 logic levels.
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Constraint Details:
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9.294ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.909ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_22:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.520 R8C15C.Q0 to R9C14D.A0 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14D.A0 to R9C14D.F0 myIwm/SLICE_37
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ROUTE 1 1.535 R9C14D.F0 to R9C14D.B1 myIwm/n4
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CTOF_DEL --- 0.495 R9C14D.B1 to R9C14D.F1 myIwm/SLICE_37
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ROUTE 3 1.749 R9C14D.F1 to R8C13C.B0 myIwm/n87
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CTOF_DEL --- 0.495 R8C13C.B0 to R8C13C.F0 myIwm/SLICE_41
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ROUTE 1 0.967 R8C13C.F0 to R8C13B.A1 myIwm/n9
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CTOF_DEL --- 0.495 R8C13B.A1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.091 R8C13B.F1 to R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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9.294 (26.2% logic, 73.8% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_22:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R9C13C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.207ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i4 (to fclk_c +)
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FF myIwm/shifter_i0_i3
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Delay: 8.592ns (28.3% logic, 71.7% route), 5 logic levels.
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Constraint Details:
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8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_20 exceeds
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6.667ns delay constraint less
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0.000ns skew and
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_20:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.954 R8C15C.Q0 to R9C14C.B1 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14C.B1 to R9C14C.F1 myIwm/SLICE_39
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ROUTE 3 0.984 R9C14C.F1 to R9C14A.A1 myIwm/n10
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CTOF_DEL --- 0.495 R9C14A.A1 to R9C14A.F1 myIwm/SLICE_38
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ROUTE 4 1.474 R9C14A.F1 to R8C13B.B0 myIwm/n1862
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CTOF_DEL --- 0.495 R8C13B.B0 to R8C13B.F0 myIwm/SLICE_36
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ROUTE 8 0.643 R8C13B.F0 to R8C13B.D1 myIwm/n163
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CTOF_DEL --- 0.495 R8C13B.D1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.105 R8C13B.F1 to R10C13B.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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8.592 (28.3% logic, 71.7% route), 5 logic levels.
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Clock Skew Details:
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Source Clock Path fclk to myIwm/SLICE_7:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Destination Clock Path fclk to myIwm/SLICE_20:
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Name Fanout Delay (ns) Site Resource
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ROUTE 27 2.264 63.PADDI to R10C13B.CLK fclk_c
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--------
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2.264 (0.0% logic, 100.0% route), 0 logic levels.
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Error: The following path exceeds requirements by 2.207ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
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Destination: FF Data in myIwm/shifter_i0_i6 (to fclk_c +)
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FF myIwm/shifter_i0_i5
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Delay: 8.592ns (28.3% logic, 71.7% route), 5 logic levels.
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Constraint Details:
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8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_21 exceeds
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|
6.667ns delay constraint less
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|
0.000ns skew and
|
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0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
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Physical Path Details:
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Data path myIwm/SLICE_7 to myIwm/SLICE_21:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
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ROUTE 8 1.954 R8C15C.Q0 to R9C14C.B1 myIwm/bitTimer_2
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CTOF_DEL --- 0.495 R9C14C.B1 to R9C14C.F1 myIwm/SLICE_39
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ROUTE 3 0.984 R9C14C.F1 to R9C14A.A1 myIwm/n10
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CTOF_DEL --- 0.495 R9C14A.A1 to R9C14A.F1 myIwm/SLICE_38
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ROUTE 4 1.474 R9C14A.F1 to R8C13B.B0 myIwm/n1862
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CTOF_DEL --- 0.495 R8C13B.B0 to R8C13B.F0 myIwm/SLICE_36
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ROUTE 8 0.643 R8C13B.F0 to R8C13B.D1 myIwm/n163
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CTOF_DEL --- 0.495 R8C13B.D1 to R8C13B.F1 myIwm/SLICE_36
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ROUTE 5 1.105 R8C13B.F1 to R10C13D.CE myIwm/fclk_c_enable_14 (to fclk_c)
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--------
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8.592 (28.3% logic, 71.7% route), 5 logic levels.
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Clock Skew Details:
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|
|
Source Clock Path fclk to myIwm/SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_21:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R10C13D.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.207ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
|
|
Destination: FF Data in myIwm/shifter_i0_i2 (to fclk_c +)
|
|
FF myIwm/shifter_i0_i1
|
|
|
|
Delay: 8.592ns (28.3% logic, 71.7% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.592ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_19 exceeds
|
|
6.667ns delay constraint less
|
|
0.000ns skew and
|
|
0.282ns CE_SET requirement (totaling 6.385ns) by 2.207ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_7 to myIwm/SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
|
|
ROUTE 8 1.954 R8C15C.Q0 to R9C14C.B1 myIwm/bitTimer_2
|
|
CTOF_DEL --- 0.495 R9C14C.B1 to R9C14C.F1 myIwm/SLICE_39
|
|
ROUTE 3 0.984 R9C14C.F1 to R9C14A.A1 myIwm/n10
|
|
CTOF_DEL --- 0.495 R9C14A.A1 to R9C14A.F1 myIwm/SLICE_38
|
|
ROUTE 4 1.474 R9C14A.F1 to R8C13B.B0 myIwm/n1862
|
|
CTOF_DEL --- 0.495 R8C13B.B0 to R8C13B.F0 myIwm/SLICE_36
|
|
ROUTE 8 0.643 R8C13B.F0 to R8C13B.D1 myIwm/n163
|
|
CTOF_DEL --- 0.495 R8C13B.D1 to R8C13B.F1 myIwm/SLICE_36
|
|
ROUTE 5 1.105 R8C13B.F1 to R10C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
|
|
--------
|
|
8.592 (28.3% logic, 71.7% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_19:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R10C13A.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.193ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
|
|
Destination: FF Data in myIwm/shifter_i0_i7 (to fclk_c +)
|
|
|
|
Delay: 8.578ns (28.4% logic, 71.6% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_22 exceeds
|
|
6.667ns delay constraint less
|
|
0.000ns skew and
|
|
0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_7 to myIwm/SLICE_22:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
|
|
ROUTE 8 1.954 R8C15C.Q0 to R9C14C.B1 myIwm/bitTimer_2
|
|
CTOF_DEL --- 0.495 R9C14C.B1 to R9C14C.F1 myIwm/SLICE_39
|
|
ROUTE 3 0.984 R9C14C.F1 to R9C14A.A1 myIwm/n10
|
|
CTOF_DEL --- 0.495 R9C14A.A1 to R9C14A.F1 myIwm/SLICE_38
|
|
ROUTE 4 1.474 R9C14A.F1 to R8C13B.B0 myIwm/n1862
|
|
CTOF_DEL --- 0.495 R8C13B.B0 to R8C13B.F0 myIwm/SLICE_36
|
|
ROUTE 8 0.643 R8C13B.F0 to R8C13B.D1 myIwm/n163
|
|
CTOF_DEL --- 0.495 R8C13B.D1 to R8C13B.F1 myIwm/SLICE_36
|
|
ROUTE 5 1.091 R8C13B.F1 to R9C13C.CE myIwm/fclk_c_enable_14 (to fclk_c)
|
|
--------
|
|
8.578 (28.4% logic, 71.6% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_22:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R9C13C.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Error: The following path exceeds requirements by 2.193ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitTimer__i2 (from fclk_c +)
|
|
Destination: FF Data in myIwm/shifter_i0_i0 (to fclk_c +)
|
|
|
|
Delay: 8.578ns (28.4% logic, 71.6% route), 5 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
8.578ns physical path delay myIwm/SLICE_7 to myIwm/SLICE_18 exceeds
|
|
6.667ns delay constraint less
|
|
0.000ns skew and
|
|
0.282ns CE_SET requirement (totaling 6.385ns) by 2.193ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_7 to myIwm/SLICE_18:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.452 R8C15C.CLK to R8C15C.Q0 myIwm/SLICE_7 (from fclk_c)
|
|
ROUTE 8 1.954 R8C15C.Q0 to R9C14C.B1 myIwm/bitTimer_2
|
|
CTOF_DEL --- 0.495 R9C14C.B1 to R9C14C.F1 myIwm/SLICE_39
|
|
ROUTE 3 0.984 R9C14C.F1 to R9C14A.A1 myIwm/n10
|
|
CTOF_DEL --- 0.495 R9C14A.A1 to R9C14A.F1 myIwm/SLICE_38
|
|
ROUTE 4 1.474 R9C14A.F1 to R8C13B.B0 myIwm/n1862
|
|
CTOF_DEL --- 0.495 R8C13B.B0 to R8C13B.F0 myIwm/SLICE_36
|
|
ROUTE 8 0.643 R8C13B.F0 to R8C13B.D1 myIwm/n163
|
|
CTOF_DEL --- 0.495 R8C13B.D1 to R8C13B.F1 myIwm/SLICE_36
|
|
ROUTE 5 1.091 R8C13B.F1 to R9C13A.CE myIwm/fclk_c_enable_14 (to fclk_c)
|
|
--------
|
|
8.578 (28.4% logic, 71.6% route), 5 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_7:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R8C15C.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_18:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 2.264 63.PADDI to R9C13A.CLK fclk_c
|
|
--------
|
|
2.264 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Warning: 104.275MHz is the maximum frequency for this preference.
|
|
|
|
Report Summary
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY NET "fclk_c" 149.993000 MHz ; | 149.993 MHz| 104.275 MHz| 5 *
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
1 preference(marked by "*" above) not met.
|
|
|
|
----------------------------------------------------------------------------
|
|
Critical Nets | Loads| Errors| % of total
|
|
----------------------------------------------------------------------------
|
|
myIwm/fclk_c_enable_14 | 5| 58| 46.77%
|
|
| | |
|
|
myIwm/n1862 | 4| 56| 45.16%
|
|
| | |
|
|
myIwm/n163 | 8| 53| 42.74%
|
|
| | |
|
|
myIwm/n10 | 3| 51| 41.13%
|
|
| | |
|
|
myIwm/bitTimer_2 | 8| 43| 34.68%
|
|
| | |
|
|
myIwm/n87 | 3| 39| 31.45%
|
|
| | |
|
|
myIwm/n9 | 1| 33| 26.61%
|
|
| | |
|
|
myIwm/bitTimer_1 | 9| 33| 26.61%
|
|
| | |
|
|
myIwm/n4 | 1| 24| 19.35%
|
|
| | |
|
|
myIwm/n514 | 7| 23| 18.55%
|
|
| | |
|
|
myIwm/n1875 | 2| 17| 13.71%
|
|
| | |
|
|
myIwm/n1854 | 2| 17| 13.71%
|
|
| | |
|
|
myIwm/bitTimer_5 | 8| 17| 13.71%
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
Clock Domains Analysis
|
|
------------------------
|
|
|
|
Found 2 clocks:
|
|
|
|
Clock Domain: fclk_c Source: fclk.PAD Loads: 27
|
|
Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: _devsel_c Source: _devsel.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: _devsel_c Source: _devsel.PAD Loads: 13
|
|
No transfer within this clock domain is found
|
|
|
|
|
|
Timing summary (Setup):
|
|
---------------
|
|
|
|
Timing errors: 124 Score: 116771
|
|
Cumulative negative slack: 116771
|
|
|
|
Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
|
|
|
|
--------------------------------------------------------------------------------
|
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.9.0.99.2
|
|
Thu Feb 22 10:56:44 2018
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
Report Information
|
|
------------------
|
|
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o liron_fpgatop.twr -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml liron_fpgatop.ncd liron_fpgatop.prf
|
|
Design file: liron_fpgatop.ncd
|
|
Preference file: liron_fpgatop.prf
|
|
Device,speed: LCMXO2-1200HC,m
|
|
Report level: verbose report, limited to 10 items per preference
|
|
--------------------------------------------------------------------------------
|
|
|
|
BLOCK ASYNCPATHS
|
|
BLOCK RESETPATHS
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
================================================================================
|
|
Preference: FREQUENCY NET "fclk_c" 149.993000 MHz ;
|
|
565 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.307ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/rddataSync_i0 (from fclk_c +)
|
|
Destination: FF Data in myIwm/rddataSync_i1 (to fclk_c +)
|
|
|
|
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.288ns physical path delay myIwm/SLICE_42 to myIwm/SLICE_42 meets
|
|
-0.019ns M_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_42 to myIwm/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C12A.CLK to R8C12A.Q0 myIwm/SLICE_42 (from fclk_c)
|
|
ROUTE 4 0.155 R8C12A.Q0 to R8C12A.M1 myIwm/rddataSync_0 (to fclk_c)
|
|
--------
|
|
0.288 (46.2% logic, 53.8% route), 1 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C12A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_42:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C12A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/wrdata_130 (from fclk_c +)
|
|
Destination: FF Data in myIwm/wrdata_130 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_29 to myIwm/SLICE_29 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_29 to myIwm/SLICE_29:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C14B.CLK to R8C14B.Q0 myIwm/SLICE_29 (from fclk_c)
|
|
ROUTE 2 0.132 R8C14B.Q0 to R8C14B.A0 wrdata_c
|
|
CTOF_DEL --- 0.101 R8C14B.A0 to R8C14B.F0 myIwm/SLICE_29
|
|
ROUTE 1 0.000 R8C14B.F0 to R8C14B.DI0 myIwm/wrdata_N_115 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_29:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C14B.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_29:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C14B.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/clearBufferTimer_i0_i3 (from fclk_c +)
|
|
Destination: FF Data in myIwm/clearBufferTimer_i0_i3 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_14 to myIwm/SLICE_14 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_14 to myIwm/SLICE_14:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C11D.CLK to R8C11D.Q0 myIwm/SLICE_14 (from fclk_c)
|
|
ROUTE 4 0.132 R8C11D.Q0 to R8C11D.A0 myIwm/clearBufferTimer_3
|
|
CTOF_DEL --- 0.101 R8C11D.A0 to R8C11D.F0 myIwm/SLICE_14
|
|
ROUTE 1 0.000 R8C11D.F0 to R8C11D.DI0 myIwm/n69 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_14:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11D.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_14:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11D.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/clearBufferTimer_i0_i2 (from fclk_c +)
|
|
Destination: FF Data in myIwm/clearBufferTimer_i0_i2 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_13 to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C11C.CLK to R8C11C.Q1 myIwm/SLICE_13 (from fclk_c)
|
|
ROUTE 5 0.132 R8C11C.Q1 to R8C11C.A1 myIwm/clearBufferTimer_2
|
|
CTOF_DEL --- 0.101 R8C11C.A1 to R8C11C.F1 myIwm/SLICE_13
|
|
ROUTE 1 0.000 R8C11C.F1 to R8C11C.DI1 myIwm/n70 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitCounter_223__i2 (from fclk_c +)
|
|
Destination: FF Data in myIwm/bitCounter_223__i2 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_5 to myIwm/SLICE_5 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_5 to myIwm/SLICE_5:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R10C14B.CLK to R10C14B.Q0 myIwm/SLICE_5 (from fclk_c)
|
|
ROUTE 2 0.132 R10C14B.Q0 to R10C14B.A0 myIwm/bitCounter_2
|
|
CTOF_DEL --- 0.101 R10C14B.A0 to R10C14B.F0 myIwm/SLICE_5
|
|
ROUTE 1 0.000 R10C14B.F0 to R10C14B.DI0 myIwm/n18_adj_148 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_5:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14B.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_5:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14B.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/clearBufferTimer_i0_i1 (from fclk_c +)
|
|
Destination: FF Data in myIwm/clearBufferTimer_i0_i1 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_13 to myIwm/SLICE_13 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_13 to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C11C.CLK to R8C11C.Q0 myIwm/SLICE_13 (from fclk_c)
|
|
ROUTE 6 0.132 R8C11C.Q0 to R8C11C.A0 myIwm/clearBufferTimer_1
|
|
CTOF_DEL --- 0.101 R8C11C.A0 to R8C11C.F0 myIwm/SLICE_13
|
|
ROUTE 1 0.000 R8C11C.F0 to R8C11C.DI0 myIwm/n71 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_13:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitCounter_223__i1 (from fclk_c +)
|
|
Destination: FF Data in myIwm/bitCounter_223__i1 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_4 to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q1 myIwm/SLICE_4 (from fclk_c)
|
|
ROUTE 3 0.132 R10C14C.Q1 to R10C14C.A1 myIwm/bitCounter_1
|
|
CTOF_DEL --- 0.101 R10C14C.A1 to R10C14C.F1 myIwm/SLICE_4
|
|
ROUTE 1 0.000 R10C14C.F1 to R10C14C.DI1 myIwm/n19_adj_149 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.379ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitCounter_223__i0 (from fclk_c +)
|
|
Destination: FF Data in myIwm/bitCounter_223__i0 (to fclk_c +)
|
|
|
|
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.366ns physical path delay myIwm/SLICE_4 to myIwm/SLICE_4 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_4 to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 myIwm/SLICE_4 (from fclk_c)
|
|
ROUTE 4 0.132 R10C14C.Q0 to R10C14C.A0 myIwm/bitCounter_0
|
|
CTOF_DEL --- 0.101 R10C14C.A0 to R10C14C.F0 myIwm/SLICE_4
|
|
ROUTE 1 0.000 R10C14C.F0 to R10C14C.DI0 myIwm/n20 (to fclk_c)
|
|
--------
|
|
0.366 (63.9% logic, 36.1% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_4:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R10C14C.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.380ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/clearBufferTimer_i0_i0 (from fclk_c +)
|
|
Destination: FF Data in myIwm/clearBufferTimer_i0_i0 (to fclk_c +)
|
|
|
|
Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.367ns physical path delay myIwm/SLICE_12 to myIwm/SLICE_12 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.380ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_12 to myIwm/SLICE_12:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q0 myIwm/SLICE_12 (from fclk_c)
|
|
ROUTE 7 0.133 R8C11A.Q0 to R8C11A.A0 myIwm/clearBufferTimer_0
|
|
CTOF_DEL --- 0.101 R8C11A.A0 to R8C11A.F0 myIwm/SLICE_12
|
|
ROUTE 1 0.000 R8C11A.F0 to R8C11A.DI0 myIwm/clearBufferTimer_3_N_70_0 (to fclk_c)
|
|
--------
|
|
0.367 (63.8% logic, 36.2% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_12:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_12:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C11A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
|
|
Passed: The following path meets requirements by 0.381ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q myIwm/bitTimer__i0 (from fclk_c +)
|
|
Destination: FF Data in myIwm/bitTimer__i0 (to fclk_c +)
|
|
|
|
Delay: 0.368ns (63.6% logic, 36.4% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.368ns physical path delay myIwm/SLICE_6 to myIwm/SLICE_6 meets
|
|
-0.013ns DIN_HLD and
|
|
0.000ns delay constraint less
|
|
0.000ns skew requirement (totaling -0.013ns) by 0.381ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path myIwm/SLICE_6 to myIwm/SLICE_6:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.133 R8C14A.CLK to R8C14A.Q0 myIwm/SLICE_6 (from fclk_c)
|
|
ROUTE 8 0.134 R8C14A.Q0 to R8C14A.A0 myIwm/bitTimer_0
|
|
CTOF_DEL --- 0.101 R8C14A.A0 to R8C14A.F0 myIwm/SLICE_6
|
|
ROUTE 1 0.000 R8C14A.F0 to R8C14A.DI0 myIwm/n1733 (to fclk_c)
|
|
--------
|
|
0.368 (63.6% logic, 36.4% route), 2 logic levels.
|
|
|
|
Clock Skew Details:
|
|
|
|
Source Clock Path fclk to myIwm/SLICE_6:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C14A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Destination Clock Path fclk to myIwm/SLICE_6:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
ROUTE 27 0.788 63.PADDI to R8C14A.CLK fclk_c
|
|
--------
|
|
0.788 (0.0% logic, 100.0% route), 0 logic levels.
|
|
|
|
Report Summary
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
FREQUENCY NET "fclk_c" 149.993000 MHz ; | 0.000 ns| 0.307 ns| 1
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
All preferences were met.
|
|
|
|
|
|
Clock Domains Analysis
|
|
------------------------
|
|
|
|
Found 2 clocks:
|
|
|
|
Clock Domain: fclk_c Source: fclk.PAD Loads: 27
|
|
Covered under: FREQUENCY NET "fclk_c" 149.993000 MHz ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: _devsel_c Source: _devsel.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: _devsel_c Source: _devsel.PAD Loads: 13
|
|
No transfer within this clock domain is found
|
|
|
|
|
|
Timing summary (Hold):
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 565 paths, 1 nets, and 301 connections (51.72% coverage)
|
|
|
|
|
|
|
|
Timing summary (Setup and Hold):
|
|
---------------
|
|
|
|
Timing errors: 124 (setup), 0 (hold)
|
|
Score: 116771 (setup), 0 (hold)
|
|
Cumulative negative slack: 116771 (116771+0)
|
|
--------------------------------------------------------------------------------
|
|
|
|
--------------------------------------------------------------------------------
|
|
|