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https://github.com/lefticus/6502-cpp.git
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Optimize out flag-fixing code followed by ldy
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cc08629435
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@ -177,9 +177,8 @@ bool optimize_redundant_lda(std::span<mos6502> &block, const Personality &person
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// look for a literal or virtual register load into A
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// that is redundant later
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (itr->opcode == mos6502::OpCode::lda &&
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(itr->op.value.starts_with('#')
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|| is_virtual_register_op(*itr, personality))) {
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if (itr->opcode == mos6502::OpCode::lda
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&& (itr->op.value.starts_with('#') || is_virtual_register_op(*itr, personality))) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (is_opcode(*inner,
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mos6502::OpCode::tay,
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@ -257,9 +256,9 @@ bool optimize(std::vector<mos6502> &instructions, [[maybe_unused]] const Persona
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// it might make sense in the future to only insert these if determined they are needed?
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for (size_t op = 10; op < instructions.size(); ++op) {
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if (instructions[op].opcode == mos6502::OpCode::lda || instructions[op].opcode == mos6502::OpCode::bcc
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|| instructions[op].opcode == mos6502::OpCode::bcs) {
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if (instructions[op - 1].text == "; END remove if next is lda, bcc, bcs"
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|| (instructions[op - 2].text == "; END remove if next is lda, bcc, bcs"
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|| instructions[op].opcode == mos6502::OpCode::bcs || instructions[op].opcode == mos6502::OpCode::ldy) {
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if (instructions[op - 1].text == "; END remove if next is lda, bcc, bcs, ldy"
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|| (instructions[op - 2].text == "; END remove if next is lda, bcc, bcs, ldy"
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&& instructions[op - 1].type == ASMLine::Type::Directive)) {
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for (size_t inner_op = op - 1; inner_op > 1; --inner_op) {
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instructions[inner_op] =
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@ -284,9 +283,9 @@ bool optimize(std::vector<mos6502> &instructions, [[maybe_unused]] const Persona
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bool block_optimized = false;
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for (auto &block : get_optimizable_blocks(instructions)) {
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block_optimized = block_optimized || optimize_redundant_lda_after_sta(block) || optimize_dead_sta(block, personality) || optimize_dead_tax(block)
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|| optimize_redundant_ldy(block) || optimize_redundant_lda(block, personality);
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block_optimized = block_optimized || optimize_redundant_lda_after_sta(block)
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|| optimize_dead_sta(block, personality) || optimize_dead_tax(block)
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|| optimize_redundant_ldy(block) || optimize_redundant_lda(block, personality);
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}
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return block_optimized;
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}
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@ -289,7 +289,7 @@ void fixup_16_bit_N_Z_flags(std::vector<mos6502> &instructions)
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// if low order byte is negative, just load 1, this will properly set the Z flag and leave C correct
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#1"));
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instructions.emplace_back(ASMLine::Type::Label, set_flag_label);
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instructions.emplace_back(ASMLine::Type::Directive, "; END remove if next is lda, bcc, bcs");
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instructions.emplace_back(ASMLine::Type::Directive, "; END remove if next is lda, bcc, bcs, ldy");
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}
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void add_16_bit(const Personality &personality, std::vector<mos6502> &instructions, int reg, const std::string_view value)
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@ -1174,21 +1174,6 @@ int main(const int argc, const char **argv)
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disabled_optimizations += " -fvect-cost-model=cheap";
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disabled_optimizations += " -fno-version-loops-for-strides";
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*/
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// disabled_optimizations += " -fgcse-after-reload";
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// disabled_optimizations += " -fipa-cp-clone";
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// disabled_optimizations += " -floop-interchange";
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// disabled_optimizations += " -floop-unroll-and-jam";
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// disabled_optimizations += " -fpeel-loops";
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// disabled_optimizations += " -fpredictive-commoning";
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// disabled_optimizations += " -fsplit-loops";
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// disabled_optimizations += " -fsplit-paths";
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// disabled_optimizations += " -ftree-loop-distribution";
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// disabled_optimizations += " -ftree-loop-vectorize";
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// disabled_optimizations += " -ftree-partial-pre";
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// disabled_optimizations += " -ftree-slp-vectorize";
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// disabled_optimizations += " -funswitch-loops";
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// disabled_optimizations += " -fvect-cost-model=dynamic";
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// disabled_optimizations += " -fversion-loops-for-strides";
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const std::string gcc_command = fmt::format(
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"avr-gcc -fverbose-asm -c -o {outfile} -S {warning_flags} -std=c++20 -mtiny-stack "
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