This commit is contained in:
Mark Canlas
2020-08-14 22:02:34 -04:00
parent b0b38f2e51
commit e98e5d7aa8
4 changed files with 6 additions and 6 deletions
@@ -94,7 +94,7 @@ class CPU {
registers.A
def A_=[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit =
ctx.push(LDA, x, "set A to value " + ev.toString(x))
ctx.push(LDA, x, "set A to value " + ev.toAddressLiteral(x))
def A_=(reg: registers.DestinationA)(implicit ctx: AssemblyContext): Unit =
reg match {
@@ -9,7 +9,7 @@ object GlobalAddress {
case class GlobalAddress(n: Int) {
def write[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit = {
ctx.push(LDA, x, s"write value ${ev.toString(x)} to address $n")
ctx.push(LDA, x, s"write value ${ev.toAddressLiteral(x)} to address $n")
ctx.push(STA, this, "")
}
}
@@ -3,7 +3,7 @@ package com.htmlism.mos6502.dsl
import cats.Contravariant
trait Operand[A] {
def toString(x: A): String
def toAddressLiteral(x: A): String
}
object Operand {
@@ -13,8 +13,8 @@ object Operand {
implicit val contra: Contravariant[Operand] = new Contravariant[Operand] {
def contramap[A, B](fa: Operand[A])(f: B => A): Operand[B] =
new Operand[B] {
def toString(x: B): String =
fa.toString {
def toAddressLiteral(x: B): String =
fa.toAddressLiteral {
f(x)
}
}
@@ -26,7 +26,7 @@ case class InstructionWithOperand[A](instruction: Instruction, operand: A, comme
instruction.toString
val operandStr =
ev.toString(operand)
ev.toAddressLiteral(operand)
comment match {
case Some(c) =>