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spell out logic
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@ -8,9 +8,10 @@ case object ZeroPageX extends AddressingMode
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case object Absolute extends AddressingMode
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case object AbsoluteX extends AddressingMode
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case object AbsoluteY extends AddressingMode
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case object Indirect extends AddressingMode // used by jump
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case object IndirectX extends AddressingMode
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case object IndirectY extends AddressingMode
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case object Relative extends AddressingMode
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case object Relative extends AddressingMode // used by branches
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case object Accumulator extends AddressingMode
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case object Implied extends AddressingMode
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case object NoMode extends AddressingMode
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@ -18,6 +18,12 @@ object MatchOpcodes {
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.toMap
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// format: off
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def injectedOpcodesJump: Map[Int, (Instruction, AddressingMode)] =
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Map(
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0x4C -> (JMP -> Absolute),
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0x6C -> (JMP -> Indirect),
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)
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def injectedOpcodesRelative: Map[Int, (Instruction, AddressingMode)] =
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Map(
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0x10 -> BPL,
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@ -68,7 +74,8 @@ object MatchOpcodes {
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val lookup =
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generatedOpcodes ++
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injectedOpcodesImplied ++
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injectedOpcodesRelative
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injectedOpcodesRelative ++
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injectedOpcodesJump
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out.print("<table>")
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@ -263,12 +270,24 @@ object MatchOpcodes {
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def c00(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
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val instruction =
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Seq(NoInstruction, BIT, JMP, JMP, STY, LDY, CPY, CPX)(aaa)
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Seq(NoInstruction, BIT, NoInstruction, NoInstruction, STY, LDY, CPY, CPX)(aaa)
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val addressingMode =
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Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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instruction match {
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case BIT =>
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Seq(NoMode, ZeroPage, NoMode, Absolute, NoMode, NoMode, NoMode, NoMode)(bbb)
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if (addressingMode == NoMode)
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case STY =>
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Seq(NoMode, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, NoMode)(bbb)
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case LDY =>
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Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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case _ =>
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Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, NoMode, NoMode, NoMode)(bbb)
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}
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if (instruction == NoInstruction || addressingMode == NoMode)
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None
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else
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(instruction -> addressingMode).some
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