mirror of
https://github.com/Klaus2m5/6502_65C02_functional_tests.git
synced 2024-12-09 21:49:16 +00:00
added report to standard output option
This commit is contained in:
Klaus2m5
parent
12434a8e47
commit
2c6a266d5f
@ -21,7 +21,7 @@
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; addressing modes with focus on propper setting of the processor status
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; register bits.
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;
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; version 23-jul-2013
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; version 16-aug-2013
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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@ -65,35 +65,47 @@
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; 02-mar-2013 fixed PLA flags not tested
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; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0
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; added test sequence check to detect if tests jump their fence
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; 23-jul-2013 added RAM integrity check
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; 23-jul-2013 added RAM integrity check option
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; 16-aug-2013 added error report to standard output option
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; C O N F I G U R A T I O N
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;
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;ROM_vectors writable (0=no, 1=yes)
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;if ROM vectors can not be used interrupts will not be trapped
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;as a consequence BRK can not be tested but will be emulated to test RTI
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ROM_vectors = 1
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;load_data_direct (0=move from code segment, 1=load directly)
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;loading directly is preferred but may not be supported by your platform
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;0 produces only consecutive object code, 1 is not suitable for a binary image
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load_data_direct = 1
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;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
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;change) 2 requires extra code and is not recommended. SEI & CLI can only be
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;tested if you allow changing the interrupt status (I_flag = 3)
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I_flag = 3
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;configure memory - try to stay away from memory used by the system
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;zero_page memory start address, $50 (80) consecutive Bytes required
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; add 2 if I_flag = 2
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zero_page = $a
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;data_segment memory start address, $5B (91) consecutive Bytes required
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data_segment = $200
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if (data_segment & $ff) != 0
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ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
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endif
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;code_segment memory start address, 13kB of consecutive space required
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; add 2.5 kB if I_flag = 2
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;parts of the code are self modifying and must reside in RAM
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code_segment = $400
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;report errors through I/O channel (0=use standard self trap loops, 1=include
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;report.i65 as I/O channel, add 3.5 kB)
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report = 0
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;RAM integrity test option. Checks for undesired RAM writes.
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;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
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;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
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@ -115,6 +127,7 @@ ram_top = -1
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; my_error_handler should pop the calling address from the stack and report it.
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; putting larger portions of code (more than 3 bytes) inside the trap macro
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; may lead to branch range problems for some tests.
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if report = 0
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trap macro
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jmp * ;failed anyway
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endm
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@ -142,9 +155,62 @@ trap_vs macro
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trap_vc macro
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bvc * ;failed overflow clear
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jmp * ;test passed, no errors
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endm
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endif
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if report = 1
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trap macro
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jsr report_error
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endm
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trap_eq macro
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bne skip\?
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trap ;failed equal (zero)
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skip\?
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endm
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trap_ne macro
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beq skip\?
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trap ;failed not equal (non zero)
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skip\?
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endm
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trap_cs macro
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bcc skip\?
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trap ;failed carry set
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skip\?
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endm
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trap_cc macro
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bcs skip\?
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trap ;failed carry clear
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skip\?
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endm
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trap_mi macro
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bpl skip\?
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trap ;failed minus (bit 7 set)
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skip\?
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endm
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trap_pl macro
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bmi skip\?
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trap ;failed plus (bit 7 clear)
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skip\?
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endm
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trap_vs macro
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bvc skip\?
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trap ;failed overflow set
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skip\?
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endm
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trap_vc macro
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bvs skip\?
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trap ;failed overflow clear
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skip\?
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jsr report_success
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endm
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endif
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carry equ %00000001 ;flag bits in status
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@ -465,7 +531,7 @@ next_test macro ;make sure, tests don't jump the fence
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cmp #test_num
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trap_ne ;test is out of sequence
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test_num = test_num + 1
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lda #test_num ;*** this tests' number
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lda #test_num ;*** next tests' number
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sta test_case
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;check_ram ;uncomment to find altered RAM after each test
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endm
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@ -491,7 +557,7 @@ ad1 ds 1 ;operand 1 - accumulator
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ad2 ds 1 ;operand 2 - memory / immediate
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adrl ds 1 ;expected result bits 0-7
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adrh ds 1 ;expected result bit 8 (carry)
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adrf ds 1 ;expected flags NV0000ZC (-V in decimal mode)
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adrf ds 1 ;expected flags NV0000ZC (only binary mode)
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sb2 ds 1 ;operand 2 complemented for subtract
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zp_bss
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zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
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@ -577,6 +643,8 @@ data_bss_end
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code
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org code_segment
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start cld
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ldx #$ff
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txs
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lda #0 ;*** test 0 = initialize
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sta test_case
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test_num = 0
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@ -586,6 +654,11 @@ test_num = 0
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sei
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endif
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;initialize I/O for report channel
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if report = 1
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jsr report_init
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endif
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;initialize BSS segment
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if load_data_direct != 1
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ldx #zp_end-zp_init-1
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@ -1036,10 +1109,6 @@ br4 php
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bvs nbr12
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bcs nbr13
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beq nbr14
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trap_mi
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trap_vs
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trap_cs
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trap_eq
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bpl br11 ;branches should be taken
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trap
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br11 bvc br12
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@ -1061,22 +1130,151 @@ br14 php
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cmp_flag 0 ;flags off except break (pushed by sw) + reserved?
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trap_ne
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;crosscheck flags
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set_stat carry
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trap_cc
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set_stat zero
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trap_ne
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set_stat overfl
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trap_vc
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bne brzs1
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beq brzs2
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brzs1
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trap ;branch zero/non zero
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brzs2 bcs brzs3
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bcc brzs4
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brzs3
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trap ;branch carry/no carry
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brzs4 bmi brzs5
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bpl brzs6
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brzs5
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trap ;branch minus/plus
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brzs6 bvs brzs7
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bvc brzs8
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brzs7
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trap ;branch overflow/no overflow
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brzs8
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set_stat carry
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beq brcs1
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bne brcs2
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brcs1
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trap ;branch zero/non zero
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brcs2 bcc brcs3
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bcs brcs4
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brcs3
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trap ;branch carry/no carry
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brcs4 bmi brcs5
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bpl brcs6
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brcs5
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trap ;branch minus/plus
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brcs6 bvs brcs7
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bvc brcs8
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brcs7
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trap ;branch overflow/no overflow
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brcs8
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set_stat minus
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trap_pl
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set_stat $ff-carry
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trap_cs
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beq brmi1
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bne brmi2
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brmi1
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trap ;branch zero/non zero
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brmi2 bcs brmi3
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bcc brmi4
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brmi3
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trap ;branch carry/no carry
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brmi4 bpl brmi5
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bmi brmi6
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brmi5
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trap ;branch minus/plus
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brmi6 bvs brmi7
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bvc brmi8
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brmi7
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trap ;branch overflow/no overflow
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brmi8
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set_stat overfl
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beq brvs1
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bne brvs2
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brvs1
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trap ;branch zero/non zero
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brvs2 bcs brvs3
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bcc brvs4
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brvs3
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trap ;branch carry/no carry
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brvs4 bmi brvs5
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bpl brvs6
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brvs5
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trap ;branch minus/plus
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brvs6 bvc brvs7
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bvs brvs8
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brvs7
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trap ;branch overflow/no overflow
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brvs8
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set_stat $ff-zero
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trap_eq
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set_stat $ff-overfl
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trap_vs
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beq brzc1
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bne brzc2
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brzc1
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trap ;branch zero/non zero
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brzc2 bcc brzc3
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bcs brzc4
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brzc3
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trap ;branch carry/no carry
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brzc4 bpl brzc5
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bmi brzc6
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brzc5
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trap ;branch minus/plus
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brzc6 bvc brzc7
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bvs brzc8
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brzc7
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trap ;branch overflow/no overflow
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brzc8
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set_stat $ff-carry
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bne brcc1
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beq brcc2
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brcc1
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trap ;branch zero/non zero
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brcc2 bcs brcc3
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bcc brcc4
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brcc3
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trap ;branch carry/no carry
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brcc4 bpl brcc5
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bmi brcc6
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brcc5
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trap ;branch minus/plus
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brcc6 bvc brcc7
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bvs brcc8
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brcc7
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trap ;branch overflow/no overflow
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brcc8
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set_stat $ff-minus
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trap_mi
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bne brpl1
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beq brpl2
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brpl1
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trap ;branch zero/non zero
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brpl2 bcc brpl3
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bcs brpl4
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brpl3
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trap ;branch carry/no carry
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brpl4 bmi brpl5
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bpl brpl6
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brpl5
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trap ;branch minus/plus
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brpl6 bvc brpl7
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bvs brpl8
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brpl7
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trap ;branch overflow/no overflow
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brpl8
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set_stat $ff-overfl
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bne brvc1
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beq brvc2
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brvc1
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trap ;branch zero/non zero
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brvc2 bcc brvc3
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bcs brvc4
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brvc3
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trap ;branch carry/no carry
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brvc4 bpl brvc5
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bmi brvc6
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brvc5
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trap ;branch minus/plus
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brvc6 bvs brvc7
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bvc brvc8
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brvc7
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trap ;branch overflow/no overflow
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brvc8
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next_test
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; test PHA does not alter flags or accumulator but PLA does
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@ -4912,7 +5110,9 @@ tdad7 cld
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lda test_case
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cmp #test_num
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trap_ne ;test is out of sequence
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trap_ne ;previous test is out of sequence
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lda #$f0 ;mark opcode testing complete
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sta test_case
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; final RAM integrity test
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; verifies that none of the previous tests has altered RAM outside of the
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@ -4925,12 +5125,12 @@ tdad7 cld
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; allowed during previous tests.
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; S U C C E S S ************************************************
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; -------------
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success ;if you get here everything went well
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; -------------
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; S U C C E S S ************************************************
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; S U C C E S S ************************************************
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jmp start ;run again
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; core subroutine of the decimal add/subtract test
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; *** WARNING - tests documented behavior only! ***
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@ -5479,7 +5679,7 @@ irq_trap ;BRK test or unextpected BRK or IRQ
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cmp_flag 0 ;break test should have B=1
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trap_ne ; - no break flag on stack
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pla
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cmp #$34 ;should have added interrupt disable
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cmp #fai ;should have added interrupt disable
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trap_ne
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tsx
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cpx #$fc ;sp -3? (return addr, flags)
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@ -5498,6 +5698,10 @@ irq_trap ;BRK test or unextpected BRK or IRQ
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rti
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trap ;runover protection
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if report = 1
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include "report.i65"
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endif
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;copy of data to initialize BSS segment
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if load_data_direct != 1
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zp_init
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@ -20,7 +20,7 @@
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; This program is designed to test IRQ and NMI of a 6502 emulator. It requires
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; an internal or external feedback register to the IRQ & NMI inputs
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;
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; version 19-jul-2013
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; version 16-aug-2013
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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@ -48,6 +48,8 @@
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;
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; versions:
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; 19-jul-2013 1st version distributed for testing
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; 16-aug-2013 added error report to standard output option
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; C O N F I G U R A T I O N
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;
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@ -86,6 +88,10 @@ data_segment = $200
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;code_segment memory start address
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code_segment = $400
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;report errors through I/O channel (0=use standard self trap loops, 1=include
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;report.i65 as I/O channel)
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report = 0
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noopt ;do not take shortcuts
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;macros for error & success traps to allow user modification
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@ -98,6 +104,11 @@ code_segment = $400
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; trap ;failed equal (zero)
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;skip\?
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; endm
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;
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; my_error_handler should pop the calling address from the stack and report it.
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; putting larger portions of code (more than 3 bytes) inside the trap macro
|
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; may lead to branch range problems for some tests.
|
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if report = 0
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trap macro
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jmp * ;failed anyway
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endm
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@ -107,9 +118,32 @@ trap_eq macro
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trap_ne macro
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bne * ;failed not equal (non zero)
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jmp * ;test passed, no errors
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endm
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endif
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if report = 1
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trap macro
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jsr report_error
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endm
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trap_eq macro
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bne skip\?
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trap ;failed equal (zero)
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skip\?
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endm
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trap_ne macro
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beq skip\?
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trap ;failed not equal (non zero)
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skip\?
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
|
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success macro
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jsr report_success
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endm
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endif
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carry equ %00000001 ;flag bits in status
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@ -156,26 +190,27 @@ set_stat macro ;setting flags in the processor status register
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endif
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org zero_page
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;BRK, IRQ, NMI test interrupt save
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zpt
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irq_a ds 1 ;a register
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irq_x ds 1 ;x register
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irq_f ds 1 ;flags
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nmi_a ds 1 ;a register
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nmi_x ds 1 ;x register
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nmi_f ds 1 ;flags
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zp_bss
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;fixed stack locations
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lst_f equ $1fe ;last flags before interrupt
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lst_a equ $1ff ;last accumulator before interrupt
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org data_segment
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data_bss
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;concurrent NMI, IRQ & BRK test result
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nmi_count ds 1 ;lowest number handled first, $ff = never
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irq_count ds 1 ;separation-1 = instructions between interrupts
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brk_count ds 1
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;expected interrupt mask
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I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI
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data_bss_end
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data_bss
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code
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org code_segment
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@ -184,6 +219,11 @@ start cld
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sta I_src
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ldx #$ff
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txs
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;initialize I/O for report channel
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if report = 1
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jsr report_init
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endif
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; load system vectors
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if load_data_direct != 1
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@ -781,6 +821,7 @@ I_clr macro ibit ;ibit = interrupt bit
|
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; S U C C E S S ************************************************
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; check data_segment +0 to +2 for sequence of concurrent interrupts
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; e.g. 0x200 = NMI, 0x201 = IRQ, 0x202 = BRK, lower values = earlier
|
||||
jmp start ;run again
|
||||
|
||||
; manual tests for the WAI opcode of the 65c02
|
||||
|
||||
@ -788,7 +829,7 @@ wai macro
|
||||
db $cb ;WAI opcode
|
||||
endm
|
||||
|
||||
; requires single step operation
|
||||
; requires single step operation, report = 0
|
||||
; set PC to the 1st instruction of the test
|
||||
; step to the WAI opcode, then manually tie the IRQ input low
|
||||
; continue to step until you see the PC advance, then remove IRQ
|
||||
@ -948,6 +989,11 @@ brk_trap
|
||||
lda #'K' ;mark (BR)K
|
||||
plp ;should be reversed by rti
|
||||
rti
|
||||
|
||||
if report = 1
|
||||
rep_int = 1
|
||||
include "report.i65"
|
||||
endif
|
||||
|
||||
|
||||
;system vectors
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
; The 6502_functional_test is a prerequisite to this test.
|
||||
; NMI, IRQ, BRK, STP & WAI are covered in the 6502_interrupt_test.
|
||||
;
|
||||
; version 23-jul-2013
|
||||
; version 16-aug-2013
|
||||
; contact info at http://2m5.de or email K@2m5.de
|
||||
;
|
||||
; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
|
||||
@ -60,39 +60,53 @@
|
||||
; 19-jul-2013 1st version distributed for testing
|
||||
; 23-jul-2013 fixed BRA out of range due to larger trap macros
|
||||
; added RAM integrity check
|
||||
; 16-aug-2013 added error report to standard output option
|
||||
|
||||
|
||||
; C O N F I G U R A T I O N
|
||||
;
|
||||
|
||||
;ROM_vectors writable (0=no, 1=yes)
|
||||
;if ROM vectors can not be used interrupts will not be trapped
|
||||
;as a consequence BRK can not be tested but will be emulated to test RTI
|
||||
ROM_vectors = 1
|
||||
|
||||
;load_data_direct (0=move from code segment, 1=load directly)
|
||||
;loading directly is preferred but may not be supported by your platform
|
||||
;0 produces only consecutive object code, 1 is not suitable for a binary image
|
||||
load_data_direct = 1
|
||||
|
||||
;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
|
||||
;change) 2 requires extra code and is not recommended.
|
||||
I_flag = 3
|
||||
|
||||
;configure memory - try to stay away from memory used by the system
|
||||
;zero_page memory start address, $4e (78) consecutive Bytes required
|
||||
; add 2 if I_flag = 2
|
||||
zero_page = $a
|
||||
|
||||
;data_segment memory start address, $5D (93) consecutive Bytes required
|
||||
; + 12 Bytes at data_segment + $f9 (JMP indirect page cross test)
|
||||
data_segment = $200
|
||||
if (data_segment & $ff) != 0
|
||||
ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
|
||||
endif
|
||||
|
||||
;code_segment memory start address, 10kB of consecutive space required
|
||||
; add 1 kB if I_flag = 2
|
||||
;parts of the code are self modifying and must reside in RAM
|
||||
code_segment = $400
|
||||
|
||||
;added WDC only opcodes WAI & STP (0=test as NOPs, >0=no test)
|
||||
wdc_op = 1
|
||||
|
||||
;added Rockwell & WDC opcodes BBR, BBS, RMB & SMB
|
||||
;(0=test as NOPs, 1=full test, >1=no test)
|
||||
rkwl_wdc_op = 1
|
||||
|
||||
;report errors through I/O channel (0=use standard self trap loops, 1=include
|
||||
;report.i65 as I/O channel, add 3 kB)
|
||||
report = 0
|
||||
|
||||
;RAM integrity test option. Checks for undesired RAM writes.
|
||||
;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
|
||||
;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
|
||||
@ -114,6 +128,7 @@ ram_top = -1
|
||||
; my_error_handler should pop the calling address from the stack and report it.
|
||||
; putting larger portions of code (more than 3 bytes) inside the trap macro
|
||||
; may lead to branch range problems for some tests.
|
||||
if report = 0
|
||||
trap macro
|
||||
jmp * ;failed anyway
|
||||
endm
|
||||
@ -141,9 +156,62 @@ trap_vs macro
|
||||
trap_vc macro
|
||||
bvc * ;failed overflow clear
|
||||
endm
|
||||
; please observe that during the test the stack gets invalidated
|
||||
; therefore a RTS inside the success macro is not possible
|
||||
success macro
|
||||
jmp * ;test passed, no errors
|
||||
endm
|
||||
endif
|
||||
if report = 1
|
||||
trap macro
|
||||
jsr report_error
|
||||
endm
|
||||
trap_eq macro
|
||||
bne skip\?
|
||||
trap ;failed equal (zero)
|
||||
skip\?
|
||||
endm
|
||||
trap_ne macro
|
||||
beq skip\?
|
||||
trap ;failed not equal (non zero)
|
||||
skip\?
|
||||
endm
|
||||
trap_cs macro
|
||||
bcc skip\?
|
||||
trap ;failed carry set
|
||||
skip\?
|
||||
endm
|
||||
trap_cc macro
|
||||
bcs skip\?
|
||||
trap ;failed carry clear
|
||||
skip\?
|
||||
endm
|
||||
trap_mi macro
|
||||
bpl skip\?
|
||||
trap ;failed minus (bit 7 set)
|
||||
skip\?
|
||||
endm
|
||||
trap_pl macro
|
||||
bmi skip\?
|
||||
trap ;failed plus (bit 7 clear)
|
||||
skip\?
|
||||
endm
|
||||
trap_vs macro
|
||||
bvc skip\?
|
||||
trap ;failed overflow set
|
||||
skip\?
|
||||
endm
|
||||
trap_vc macro
|
||||
bvs skip\?
|
||||
trap ;failed overflow clear
|
||||
skip\?
|
||||
endm
|
||||
; please observe that during the test the stack gets invalidated
|
||||
; therefore a RTS inside the success macro is not possible
|
||||
success macro
|
||||
jsr report_success
|
||||
endm
|
||||
endif
|
||||
|
||||
|
||||
carry equ %00000001 ;flag bits in status
|
||||
@ -472,7 +540,7 @@ next_test macro ;make sure, tests don't jump the fence
|
||||
cmp #test_num
|
||||
trap_ne ;test is out of sequence
|
||||
test_num = test_num + 1
|
||||
lda #test_num ;*** this tests' number
|
||||
lda #test_num ;*** next tests' number
|
||||
sta test_case
|
||||
;check_ram ;uncomment to find altered RAM after each test
|
||||
endm
|
||||
@ -582,9 +650,12 @@ jxi_tab equ data_segment + $100 - 7 ;JMP (jxi_tab,x) x=6
|
||||
ji_tab equ data_segment + $100 - 3 ;JMP (ji_tab+2)
|
||||
jxp_tab equ data_segment + $100 ;JMP (jxp_tab-255) x=255
|
||||
|
||||
|
||||
code
|
||||
org code_segment
|
||||
start cld
|
||||
ldx #$ff
|
||||
txs
|
||||
lda #0 ;*** test 0 = initialize
|
||||
sta test_case
|
||||
test_num = 0
|
||||
@ -594,6 +665,11 @@ test_num = 0
|
||||
sei
|
||||
endif
|
||||
|
||||
;initialize I/O for report channel
|
||||
if report = 1
|
||||
jsr report_init
|
||||
endif
|
||||
|
||||
;initialize BSS segment
|
||||
if load_data_direct != 1
|
||||
ldx #zp_end-zp_init-1
|
||||
@ -2129,7 +2205,9 @@ tdad7 cpx #ad2
|
||||
|
||||
lda test_case
|
||||
cmp #test_num
|
||||
trap_ne ;test is out of sequence
|
||||
trap_ne ;previous test is out of sequence
|
||||
lda #$f0 ;mark opcode testing complete
|
||||
sta test_case
|
||||
|
||||
; final RAM integrity test
|
||||
; verifies that none of the previous tests has altered RAM outside of the
|
||||
@ -2142,12 +2220,12 @@ tdad7 cpx #ad2
|
||||
; allowed during previous tests.
|
||||
|
||||
|
||||
|
||||
; S U C C E S S ************************************************
|
||||
; -------------
|
||||
success ;if you get here everything went well
|
||||
; -------------
|
||||
; S U C C E S S ************************************************
|
||||
jmp start ;run again
|
||||
|
||||
; core subroutine of the decimal add/subtract test
|
||||
; *** WARNING - tests documented behavior only! ***
|
||||
@ -2529,6 +2607,10 @@ irq_trap
|
||||
else
|
||||
trap_ne ;check stack for conditions at BRK
|
||||
endif
|
||||
|
||||
if report = 1
|
||||
include "report.i65"
|
||||
endif
|
||||
|
||||
;copy of data to initialize BSS segment
|
||||
if load_data_direct != 1
|
||||
|
||||
@ -21,7 +21,7 @@ project. You can find it here: http://2m5.de/6502_Emu/index.htm
|
||||
A discussion about the tests can be found here:
|
||||
http://forum.6502.org/viewtopic.php?f=2&t=2241
|
||||
|
||||
Good luck debugging your emulator, simulator, vhdl core, discrete
|
||||
Good luck debugging your emulator, simulator, fpga core, discrete
|
||||
logic implementation or whatever you have!
|
||||
|
||||
|
||||
|
||||
179
report.i65
Normal file
179
report.i65
Normal file
@ -0,0 +1,179 @@
|
||||
;**** report 6502 funtional test errors to standard I/O ****
|
||||
;
|
||||
;this include file is part of the 6502 functional tests
|
||||
;it is used when you configure report = 1 in the tests
|
||||
;
|
||||
;to adopt the standard output vectors of your test environment
|
||||
;you must modify the rchar and rget subroutines in this include
|
||||
;
|
||||
;I/O hardware may have to be initialized in report_init
|
||||
|
||||
;print message macro - \1 = message location
|
||||
rprt macro
|
||||
ldx #0
|
||||
lda \1
|
||||
loop\?
|
||||
jsr rchar
|
||||
inx
|
||||
lda \1,x
|
||||
bne loop\?
|
||||
endm
|
||||
|
||||
;initialize I/O as required (example: configure & enable ACIA)
|
||||
report_init
|
||||
;nothing to initialize
|
||||
rprt rmsg_start
|
||||
rts
|
||||
|
||||
;show stack (with saved registers), zeropage and absolute memory workspace
|
||||
;after an error was trapped in the test program
|
||||
report_error
|
||||
;save registers
|
||||
php
|
||||
pha
|
||||
txa
|
||||
pha
|
||||
tya
|
||||
pha
|
||||
cld
|
||||
;show stack with index to registers at error
|
||||
rprt rmsg_stack
|
||||
tsx
|
||||
inx
|
||||
lda #1 ;address high
|
||||
jsr rhex
|
||||
txa ;address low
|
||||
jsr rhex
|
||||
rstack jsr rspace
|
||||
lda $100,x ;stack data
|
||||
jsr rhex
|
||||
inx
|
||||
bne rstack
|
||||
jsr rcrlf ;new line
|
||||
;show zero page workspace
|
||||
lda #0
|
||||
jsr rhex
|
||||
lda #zpt
|
||||
tax
|
||||
jsr rhex
|
||||
rzp jsr rspace
|
||||
lda 0,x
|
||||
jsr rhex
|
||||
inx
|
||||
cpx #zp_bss
|
||||
bne rzp
|
||||
jsr rcrlf
|
||||
;show absolute workspace
|
||||
lda #hi(data_segment)
|
||||
jsr rhex
|
||||
lda #lo(data_segment)
|
||||
jsr rhex
|
||||
ldx #0
|
||||
rabs jsr rspace
|
||||
lda data_segment,x
|
||||
jsr rhex
|
||||
inx
|
||||
cpx #(data_bss-data_segment)
|
||||
bne rabs
|
||||
;ask to continue
|
||||
rprt rmsg_cont
|
||||
rerr1 jsr rget
|
||||
cmp #'C'
|
||||
bne rerr1
|
||||
;restore registers
|
||||
pla
|
||||
tay
|
||||
pla
|
||||
tax
|
||||
pla
|
||||
plp
|
||||
rts
|
||||
|
||||
;show test has ended, ask to repeat
|
||||
report_success
|
||||
if rep_int = 1
|
||||
rprt rmsg_priority
|
||||
lda data_segment ;show interrupt sequence
|
||||
jsr rhex
|
||||
jsr rspace
|
||||
lda data_segment+1
|
||||
jsr rhex
|
||||
jsr rspace
|
||||
lda data_segment+2
|
||||
jsr rhex
|
||||
endif
|
||||
rprt rmsg_success
|
||||
rsuc1 jsr rget
|
||||
cmp #'R'
|
||||
bne rsuc1
|
||||
rts
|
||||
|
||||
;input subroutine
|
||||
;get a character from standard input
|
||||
;adjust according to the needs in your test environment
|
||||
rget ;get character in A
|
||||
;rget1
|
||||
; lda $bff1 ;wait RDRF
|
||||
; and #8
|
||||
; beq rget1
|
||||
;not a real ACIA - so RDRF is not checked
|
||||
lda $bff0 ;read acia rx reg
|
||||
;the load can be replaced by a call to a kernal routine
|
||||
; jsr $ffcf ;example: CHRIN for a C64
|
||||
cmp #'a' ;lower case
|
||||
bcc rget1
|
||||
and #$5f ;convert to upper case
|
||||
rget1 rts
|
||||
|
||||
;output subroutines
|
||||
rcrlf lda #10
|
||||
jsr rchar
|
||||
lda #13
|
||||
bne rchar
|
||||
|
||||
rspace lda #' '
|
||||
bne rchar
|
||||
|
||||
rhex pha ;report hex byte in A
|
||||
lsr a ;high nibble first
|
||||
lsr a
|
||||
lsr a
|
||||
lsr a
|
||||
jsr rnib
|
||||
pla ;now low nibble
|
||||
and #$f
|
||||
|
||||
rnib clc ;report nibble in A
|
||||
adc #'0' ;make printable 0-9
|
||||
cmp #'9'+1
|
||||
bcc rchar
|
||||
adc #6 ;make printable A-F
|
||||
|
||||
;send a character to standard output
|
||||
;adjust according to the needs in your test environment
|
||||
;register X needs to be preserved!
|
||||
rchar ;report character in A
|
||||
; pha ;wait TDRF
|
||||
;rchar1 lda $bff1
|
||||
; and #$10
|
||||
; beq rchar1
|
||||
; pla
|
||||
;not a real ACIA - so TDRF is not checked
|
||||
sta $bff0 ;write acia tx reg
|
||||
;the store can be replaced by a call to a kernal routine
|
||||
; jsr $ffd2 ;example: CHROUT for a C64
|
||||
rts
|
||||
|
||||
rmsg_start
|
||||
db 10,13,"Started testing",10,13,0
|
||||
rmsg_stack
|
||||
db 10,13,"regs Y X A PS PCLPCH",10,13,0
|
||||
rmsg_cont
|
||||
db 10,13,"press C to continue",10,13,0
|
||||
rmsg_success
|
||||
db 10,13,"All tests completed, press R to repeat",10,13,0
|
||||
if rep_int = 1
|
||||
rmsg_priority
|
||||
db 10,13,"interrupt sequence (NMI IRQ BRK) ",0
|
||||
endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user