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1015 lines
30 KiB
Plaintext
1015 lines
30 KiB
Plaintext
;
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; 6 5 0 2 I N T E R R U P T T E S T
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;
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; Copyright (C) 2013 Klaus Dormann
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;
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; This program is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <http://www.gnu.org/licenses/>.
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; This program is designed to test IRQ and NMI of a 6502 emulator. It requires
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; an internal or external feedback register to the IRQ & NMI inputs
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;
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; version 16-aug-2013
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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; command line switches: -l -m -s2 -w -h0
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; | | | | no page headers in listing
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; | | | wide listing (133 char/col)
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; | | write intel hex file instead of binary
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; | expand macros in listing
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; generate pass2 listing
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;
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; No IO - should be run from a monitor with access to registers.
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; To run load intel hex image with a load command, than alter PC to 400 hex and
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; enter a go command.
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; Loop on program counter determines error or successful completion of test.
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; Check listing for relevant traps (jump/branch *).
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;
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; Debugging hints:
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; Most of the code is written sequentially. if you hit a trap, check the
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; immediately preceeding code for the instruction to be tested. Results are
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; tested first, flags are checked second by pushing them onto the stack and
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; pulling them to the accumulator after the result was checked. The "real"
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; flags are no longer valid for the tested instruction at this time!
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; If the tested instruction was indexed, the relevant index (X or Y) must
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; also be checked. Opposed to the flags, X and Y registers are still valid.
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;
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; versions:
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; 19-jul-2013 1st version distributed for testing
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; 16-aug-2013 added error report to standard output option
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; C O N F I G U R A T I O N
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;
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;ROM_vectors MUST be writable & the I_flag MUST be alterable
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;load_data_direct (0=move from code segment, 1=load directly)
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;loading directly is preferred but may not be supported by your platform
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;0 produces only consecutive object code, 1 is not suitable for a binary image
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load_data_direct = 1
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;NMI & IRQ are tested with a feedback register
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;emulators diag register - set i_drive = 0 for a latch (74HC573)
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I_port = $bffc ;feedback port address
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I_ddr = 0 ;feedback DDR address, 0 = no DDR
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I_drive = 1 ;0 = totem pole, 1 = open collector
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IRQ_bit = 0 ;bit number of feedback to IRQ
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NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available
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;typical IO chip port B - set i_drive = 0 to avoid pullup resistors
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;I_port = $bfb2 ;feedback port address
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;I_ddr = $bfb3 ;feedback DDR address, 0 = no DDR
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;I_drive = 1 ;0 = totem pole, 1 = open collector
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;IRQ_bit = 0 ;bit number of feedback to IRQ
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;NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available
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;decimal mode flag during IRQ, NMI & BRK
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D_clear = 1 ;0 = not cleared (NMOS), 1 = cleared (CMOS)
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;configure memory - try to stay away from memory used by the system
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;zero_page memory start address, 6 consecutive Bytes required
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zero_page = $a
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;data_segment memory start address, 4 consecutive Bytes required
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data_segment = $200
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;code_segment memory start address
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code_segment = $400
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;report errors through I/O channel (0=use standard self trap loops, 1=include
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;report.i65 as I/O channel)
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report = 0
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noopt ;do not take shortcuts
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;macros for error & success traps to allow user modification
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;example:
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;trap macro
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; jsr my_error_handler
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; endm
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;trap_eq macro
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; bne skip\?
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; trap ;failed equal (zero)
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;skip\?
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; endm
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;
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; my_error_handler should pop the calling address from the stack and report it.
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; putting larger portions of code (more than 3 bytes) inside the trap macro
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; may lead to branch range problems for some tests.
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if report = 0
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trap macro
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jmp * ;failed anyway
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endm
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trap_eq macro
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beq * ;failed equal (zero)
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endm
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trap_ne macro
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bne * ;failed not equal (non zero)
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jmp * ;test passed, no errors
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endm
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endif
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if report = 1
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trap macro
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jsr report_error
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endm
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trap_eq macro
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bne skip\?
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trap ;failed equal (zero)
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skip\?
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endm
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trap_ne macro
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beq skip\?
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trap ;failed not equal (non zero)
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skip\?
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jsr report_success
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endm
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endif
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carry equ %00000001 ;flag bits in status
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zero equ %00000010
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intdis equ %00000100
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decmode equ %00001000
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break equ %00010000
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reserv equ %00100000
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overfl equ %01000000
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minus equ %10000000
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fc equ carry
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fz equ zero
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fzc equ carry+zero
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fv equ overfl
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fvz equ overfl+zero
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fn equ minus
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fnc equ minus+carry
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fnz equ minus+zero
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fnzc equ minus+zero+carry
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fnv equ minus+overfl
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fao equ break+reserv ;bits always on after PHP, BRK
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fai equ fao+intdis ;+ forced interrupt disable
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m8 equ $ff ;8 bit mask
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m8i equ $ff&~intdis ;8 bit mask - interrupt disable
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;macros to set status
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push_stat macro ;setting flags in the processor status register
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lda #\1
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pha ;use stack to load status
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endm
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set_stat macro ;setting flags in the processor status register
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lda #\1
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pha ;use stack to load status
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plp
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endm
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if load_data_direct = 1
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data
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else
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bss ;uninitialized segment, copy of data at end of code!
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endif
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org zero_page
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;BRK, IRQ, NMI test interrupt save
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zpt
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irq_a ds 1 ;a register
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irq_x ds 1 ;x register
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irq_f ds 1 ;flags
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nmi_a ds 1 ;a register
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nmi_x ds 1 ;x register
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nmi_f ds 1 ;flags
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zp_bss
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;fixed stack locations
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lst_f equ $1fe ;last flags before interrupt
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lst_a equ $1ff ;last accumulator before interrupt
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org data_segment
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;concurrent NMI, IRQ & BRK test result
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nmi_count ds 1 ;lowest number handled first, $ff = never
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irq_count ds 1 ;separation-1 = instructions between interrupts
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brk_count ds 1
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;expected interrupt mask
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I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI
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data_bss
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code
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org code_segment
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start cld
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lda #0 ;clear expected interrupts for 2nd run
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sta I_src
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ldx #$ff
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txs
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;initialize I/O for report channel
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if report = 1
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jsr report_init
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endif
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; load system vectors
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if load_data_direct != 1
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ldx #5
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ld_vect lda vec_init,x
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sta vec_bss,x
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dex
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bpl ld_vect
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endif
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; IRQ & NMI test - requires a feedback register
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if I_drive > 1
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ERROR ;invalid interrupt drive!
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endif
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if NMI_bit < 0
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if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt)
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I_set macro ibit ;ibit = interrupt bit
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lda I_port ;turn on interrupt by bit
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and #$ff-(1<<\1)
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plp ;set flags
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pha ;save to verify
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php
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sta I_port ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_port ;turn off interrupt by bit
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ora #(1<<ibit)
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sta I_port
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endm
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I_clr IRQ_bit ;turn off IRQ
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if I_ddr != 0 ;with DDR
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lda I_ddr ;set DDR for IRQ to enabled
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ora #(1<<IRQ_bit)
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sta I_ddr
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endif
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else ;open collector, 0 -> I_DDR or I_port to force interrupt
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if I_ddr != 0 ;with DDR
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I_set macro ibit ;ibit = interrupt bit
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lda I_ddr ;turn on interrupt by bit
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ora #(1<<\1)
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plp ;set flags
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pha ;save to verify
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php
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sta I_ddr ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_ddr ;turn off interrupt by bit
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and #$ff-(1<<ibit)
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sta I_ddr
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endm
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I_clr IRQ_bit ;turn off IRQ
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lda I_port ;precharge IRQ
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and #$ff-(1<<IRQ_bit)
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sta I_port
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else ;no DDR
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I_set macro ibit ;ibit = interrupt bit
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lda I_port ;turn on interrupt by bit
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ora #(1<<\1)
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plp ;set flags
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pha ;save to verify
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php
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sta I_port ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_port ;turn off interrupt by bit
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and #$ff-(1<<ibit)
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sta I_port
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endm
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I_clr IRQ_bit ;turn off IRQ
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endif
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endif
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else
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if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt)
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I_set macro ibit ;ibit = interrupt bit
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lda I_port ;turn on interrupt by bit
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if ibit > 7 ;set both NMI & IRQ
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and #$ff-(1<<IRQ_bit|1<<NMI_bit)
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else
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and #$ff-(1<<\1)
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endif
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plp ;set flags
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pha ;save to verify
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php
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sta I_port ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_port ;turn off interrupt by bit
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ora #(1<<ibit)
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sta I_port
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endm
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I_clr IRQ_bit ;turn off IRQ & NMI
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I_clr NMI_bit
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if I_ddr != 0 ;with DDR
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lda I_ddr ;set DDR for IRQ & NMI to enabled
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ora #(1<<IRQ_bit|1<<NMI_bit)
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sta I_ddr
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endif
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else ;open collector, 0 -> I_DDR or I_port to force interrupt
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if I_ddr != 0 ;with DDR
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I_set macro ibit ;ibit = interrupt bit
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lda I_ddr ;turn on interrupt by bit
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if ibit > 7 ;set both NMI & IRQ
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ora #(1<<IRQ_bit|1<<NMI_bit)
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else
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ora #(1<<\1)
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endif
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plp ;set flags
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pha ;save to verify
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php
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sta I_ddr ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_ddr ;turn off interrupt by bit
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and #$ff-(1<<ibit)
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sta I_ddr
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endm
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I_clr IRQ_bit ;turn off IRQ & NMI
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I_clr NMI_bit
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lda I_port ;precharge IRQ & NMI
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and #$ff-(1<<IRQ_bit|1<<NMI_bit)
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sta I_port
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else ;no DDR
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I_set macro ibit ;ibit = interrupt bit
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lda I_port ;turn on interrupt by bit
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if ibit > 7 ;set both NMI & IRQ
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ora #(1<<IRQ_bit|1<<NMI_bit)
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else
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ora #(1<<\1)
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endif
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plp ;set flags
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pha ;save to verify
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php
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sta I_port ;interrupt next instruction plus outbound delay
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endm
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I_clr macro ibit ;ibit = interrupt bit
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lda I_port ;turn off interrupt by bit
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and #$ff-(1<<ibit)
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sta I_port
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endm
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I_clr IRQ_bit ;turn off IRQ & NMI
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I_clr NMI_bit
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endif
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endif
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endif
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; IRQ integrity test
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; test for clear flags seen in IRQ vector
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lda #2 ;set expected interrupt source IRQ
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sta I_src
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push_stat 0
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I_set IRQ_bit
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nop ;allow 6 cycles for interrupt to trip
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nop
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nop
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lda I_src
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trap_ne ;IRQ timeout
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tsx
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cpx #$ff-2 ;original accu & flags remain on stack
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trap_ne ;returned SP
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lda irq_f ;flags seen in IRQ vector
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if D_clear = 1
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and #decmode
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trap_ne ;D-flag not cleared
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lda irq_f
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eor lst_f ;turn off unchanged bits
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and #m8-fai-decmode ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C) changed
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else
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eor lst_f ;turn off unchanged bits
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and #m8-fai ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C,D) changed
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endif
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ldx #$ff ;reset stack pointer
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txs
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; test all other registers
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ldx #'I'
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ldy #'R'
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lda #2 ;set expected interrupt source IRQ
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sta I_src
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push_stat 0
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I_set IRQ_bit
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dey ;Y count will fail, if instructions are skipped
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dey
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dey
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dey
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php ;check processor status later
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cpx #('I'+1) ;returned registers OK?
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trap_ne ;returned X
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cpy #('R'-7)
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trap_ne ;returned Y
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cmp #'Q'
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trap_ne ;returned A
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tsx
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cpx #$ff-3
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trap_ne ;returned SP
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pla ;flags
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eor lst_f
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and #$ff-fnz ;ignore flags changed by dey
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trap_ne ;returned flags
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lda irq_a ;accu seen in IRQ vector
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cmp lst_a
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trap_ne ;IRQ A received
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ldx #$ff ;reset stack pointer
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txs
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; repeat with reversed registers
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ldx #$ff-'I'
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ldy #$ff-'R'
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lda #2 ;set expected interrupt source IRQ
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sta I_src
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push_stat $ff-intdis
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I_set IRQ_bit
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dey ;Y count will fail, if instructions are skipped
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dey
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dey
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dey
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php ;check processor status later
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cpx #($ff-'I'+1) ;returned registers OK?
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trap_ne ;returned X
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cpy #($ff-'R'-7)
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trap_ne ;returned Y
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cmp #'Q'
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trap_ne ;returned A
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tsx
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cpx #$ff-3
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trap_ne ;returned SP
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pla ;flags
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eor lst_f
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and #$ff-fnz ;ignore flags changed by dey
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trap_ne ;returned flags
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lda irq_a ;accu seen in IRQ vector
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cmp lst_a
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trap_ne ;IRQ A received
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ldx #$ff ;reset stack pointer
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txs
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; retest for set flags seen in IRQ vector
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lda #2 ;set expected interrupt source IRQ
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sta I_src
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push_stat $ff-intdis
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I_set IRQ_bit
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nop ;allow 6 cycles for interrupt to trip
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nop
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nop
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lda I_src
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trap_ne ;IRQ timeout
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tsx
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cpx #$ff-2 ;original accu & flags remain on stack
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trap_ne ;returned SP
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lda irq_f ;flags seen in IRQ vector
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if D_clear = 1
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and #decmode
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trap_ne ;D-flag not cleared
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lda irq_f
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eor lst_f ;turn off unchanged bits
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and #m8-fai-decmode ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C) changed
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else
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eor lst_f ;turn off unchanged bits
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and #m8-fai ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C,D) changed
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endif
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ldx #$ff ;reset stack pointer
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txs
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; BRK integrity test
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; test for clear flags seen in IRQ vector
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lda #1 ;set expected interrupt source BRK
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sta I_src
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set_stat 0
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pha ;save entry registers
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php
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brk
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nop ;should not be executed
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nop ;allow 6 cycles for interrupt to trip
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nop
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nop
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lda I_src
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trap_ne ;IRQ timeout
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tsx
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cpx #$ff-2 ;original accu & flags remain on stack
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trap_ne ;returned SP
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lda irq_f ;flags seen in IRQ vector
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if D_clear = 1
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and #decmode
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trap_ne ;D-flag not cleared
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lda irq_f
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eor lst_f ;turn off unchanged bits
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and #m8-fai-decmode ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C) changed
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else
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eor lst_f ;turn off unchanged bits
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and #m8-fai ;mask untested other flags
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trap_ne ;other flags (N,V,Z,C,D) changed
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endif
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ldx #$ff ;reset stack pointer
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txs
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; test all other registers
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ldx #'B'
|
|
ldy #'R'
|
|
lda #1 ;set expected interrupt source BRK
|
|
sta I_src
|
|
set_stat 0
|
|
pha ;save entry
|
|
php
|
|
brk
|
|
dey ;should not be executed
|
|
dey ;Y count will fail, if return address is wrong
|
|
dey
|
|
dey
|
|
dey
|
|
php ;check processor status later
|
|
cpx #('B'+1) ;returned registers OK?
|
|
trap_ne ;returned X
|
|
cpy #('R'-7)
|
|
trap_ne ;returned Y
|
|
cmp #'K'
|
|
trap_ne ;returned A
|
|
tsx
|
|
cpx #$ff-3
|
|
trap_ne ;returned SP
|
|
pla ;flags
|
|
eor lst_f
|
|
and #$ff-fnz ;ignore flags changed by dey
|
|
trap_ne ;returned flags
|
|
lda irq_a ;accu seen in IRQ vector
|
|
cmp lst_a
|
|
trap_ne ;IRQ A received
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
; repeat with reversed registers
|
|
ldx #$ff-'B'
|
|
ldy #$ff-'R'
|
|
lda #1 ;set expected interrupt source BRK
|
|
sta I_src
|
|
set_stat $ff
|
|
pha ;save entry registers
|
|
php
|
|
brk
|
|
dey ;should not be executed
|
|
dey ;Y count will fail, if return address is wrong
|
|
dey
|
|
dey
|
|
dey
|
|
php ;check processor status later
|
|
cpx #($ff-'B'+1) ;returned registers OK?
|
|
trap_ne ;returned X
|
|
cpy #($ff-'R'-7)
|
|
trap_ne ;returned Y
|
|
cmp #'K'
|
|
trap_ne ;returned A
|
|
tsx
|
|
cpx #$ff-3
|
|
trap_ne ;returned SP
|
|
pla ;flags
|
|
eor lst_f
|
|
and #$ff-fnz ;ignore flags changed by dey
|
|
trap_ne ;returned flags
|
|
lda irq_a ;accu seen in IRQ vector
|
|
cmp lst_a
|
|
trap_ne ;IRQ A received
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
; retest for set flags seen in IRQ vector
|
|
lda #1 ;set expected interrupt source BRK
|
|
sta I_src
|
|
set_stat $ff
|
|
pha ;save entry registers
|
|
php
|
|
brk
|
|
nop ;should not be executed
|
|
nop ;allow 6 cycles for interrupt to trip
|
|
nop
|
|
nop
|
|
lda I_src
|
|
trap_ne ;IRQ timeout
|
|
tsx
|
|
cpx #$ff-2 ;original accu & flags remain on stack
|
|
trap_ne ;returned SP
|
|
lda irq_f ;flags seen in IRQ vector
|
|
if D_clear = 1
|
|
and #decmode
|
|
trap_ne ;D-flag not cleared
|
|
lda irq_f
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai-decmode ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C) changed
|
|
else
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C,D) changed
|
|
endif
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
|
|
if NMI_bit < 0
|
|
; test IRQ with interrupts disabled
|
|
ldx #0
|
|
lda #0
|
|
sta I_src
|
|
push_stat intdis
|
|
I_set IRQ_bit ;IRQ pending
|
|
inx
|
|
inx
|
|
inx
|
|
ldx #0
|
|
lda #2 ;now re-enable IRQ
|
|
sta I_src
|
|
cli
|
|
inx
|
|
inx
|
|
inx
|
|
lda I_src ;test IRQ done?
|
|
trap_ne
|
|
ldx #$ff ;purge stack
|
|
txs
|
|
|
|
ldx #0 ;now overlap IRQ & BRK
|
|
lda #3
|
|
sta I_src
|
|
lda #$ff ;measure timing
|
|
sta nmi_count
|
|
sta irq_count
|
|
sta brk_count
|
|
push_stat 0
|
|
I_set IRQ_bit ;trigger IRQ
|
|
else
|
|
; NMI integrity test
|
|
; test for clear flags seen in NMI vector
|
|
lda #4 ;set expected interrupt source NMI
|
|
sta I_src
|
|
push_stat 0
|
|
I_set NMI_bit
|
|
nop ;allow 6 cycles for interrupt to trip
|
|
nop
|
|
nop
|
|
lda I_src
|
|
trap_ne ;NMI timeout
|
|
tsx
|
|
cpx #$ff-2 ;original accu & flags remain on stack
|
|
trap_ne ;returned SP
|
|
lda nmi_f ;flags seen in NMI vector
|
|
if D_clear = 1
|
|
and #decmode
|
|
trap_ne ;D-flag not cleared
|
|
lda nmi_f
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai-decmode ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C) changed
|
|
else
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C,D) changed
|
|
endif
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
; test all other registers
|
|
ldx #'N'
|
|
ldy #'M'
|
|
lda #4 ;set expected interrupt source NMI
|
|
sta I_src
|
|
push_stat 0
|
|
I_set NMI_bit
|
|
dey ;Y count will fail, if instructions are skipped
|
|
dey
|
|
dey
|
|
dey
|
|
php ;check processor status later
|
|
cpx #('N'+1) ;returned registers OK?
|
|
trap_ne ;returned X
|
|
cpy #('M'-7)
|
|
trap_ne ;returned Y
|
|
cmp #'I'
|
|
trap_ne ;returned A
|
|
tsx
|
|
cpx #$ff-3
|
|
trap_ne ;returned SP
|
|
pla ;flags
|
|
eor lst_f
|
|
and #$ff-fnz ;ignore flags changed by dey
|
|
trap_ne ;returned flags
|
|
lda nmi_a ;accu seen in NMI vector
|
|
cmp lst_a
|
|
trap_ne ;NMI A received
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
; repeat with reversed registers
|
|
ldx #$ff-'N'
|
|
ldy #$ff-'M'
|
|
lda #4 ;set expected interrupt source NMI
|
|
sta I_src
|
|
push_stat $ff-intdis
|
|
I_set NMI_bit
|
|
dey ;Y count will fail, if instructions are skipped
|
|
dey
|
|
dey
|
|
dey
|
|
php ;check processor status later
|
|
cpx #($ff-'N'+1) ;returned registers OK?
|
|
trap_ne ;returned X
|
|
cpy #($ff-'M'-7)
|
|
trap_ne ;returned Y
|
|
cmp #'I'
|
|
trap_ne ;returned A
|
|
tsx
|
|
cpx #$ff-3
|
|
trap_ne ;returned SP
|
|
pla ;flags
|
|
eor lst_f
|
|
and #$ff-fnz ;ignore flags changed by dey
|
|
trap_ne ;returned flags
|
|
lda nmi_a ;accu seen in NMI vector
|
|
cmp lst_a
|
|
trap_ne ;NMI A received
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
; retest for set flags seen in NMI vector
|
|
lda #4 ;set expected interrupt source NMI
|
|
sta I_src
|
|
push_stat $ff-intdis
|
|
I_set NMI_bit
|
|
nop ;allow 6 cycles for interrupt to trip
|
|
nop
|
|
nop
|
|
lda I_src
|
|
trap_ne ;NMI timeout
|
|
tsx
|
|
cpx #$ff-2 ;original accu & flags remain on stack
|
|
trap_ne ;returned SP
|
|
lda nmi_f ;flags seen in NMI vector
|
|
if D_clear = 1
|
|
and #decmode
|
|
trap_ne ;D-flag not cleared
|
|
lda nmi_f
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai-decmode ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C) changed
|
|
else
|
|
eor lst_f ;turn off unchanged bits
|
|
and #m8-fai ;mask untested other flags
|
|
trap_ne ;other flags (N,V,Z,C,D) changed
|
|
endif
|
|
ldx #$ff ;reset stack pointer
|
|
txs
|
|
|
|
; test IRQ & NMI with interrupts disabled
|
|
ldx #0
|
|
lda #4 ;set expected interrupt NMI only
|
|
sta I_src
|
|
push_stat intdis
|
|
I_set 8 ;both interrupts pending
|
|
inx
|
|
inx
|
|
inx
|
|
lda I_src ;test NMI done?
|
|
trap_ne
|
|
ldx #0
|
|
lda #2 ;now re-enable IRQ
|
|
sta I_src
|
|
cli
|
|
inx
|
|
inx
|
|
inx
|
|
lda I_src ;test IRQ done?
|
|
trap_ne
|
|
ldx #$ff ;purge stack
|
|
txs
|
|
|
|
;test overlapping NMI, IRQ & BRK
|
|
ldx #0
|
|
lda #7
|
|
sta I_src
|
|
lda #$ff ;measure timing
|
|
sta nmi_count
|
|
sta irq_count
|
|
sta brk_count
|
|
push_stat 0
|
|
I_set 8 ;trigger NMI + IRQ
|
|
endif
|
|
brk
|
|
inx
|
|
inx
|
|
inx
|
|
inx
|
|
inx
|
|
inx
|
|
inx
|
|
inx
|
|
lda I_src ;test all done?
|
|
;may fail due to a bug on a real NMOS 6502 - NMI could mask BRK
|
|
trap_ne ;lost an interrupt
|
|
|
|
; S U C C E S S ************************************************
|
|
; -------------
|
|
success ;if you get here everything went well
|
|
; -------------
|
|
; S U C C E S S ************************************************
|
|
; check data_segment +0 to +2 for sequence of concurrent interrupts
|
|
; e.g. 0x200 = NMI, 0x201 = IRQ, 0x202 = BRK, lower values = earlier
|
|
jmp start ;run again
|
|
|
|
; manual tests for the WAI opcode of the 65c02
|
|
|
|
wai macro
|
|
db $cb ;WAI opcode
|
|
endm
|
|
|
|
; requires single step operation, report = 0
|
|
; set PC to the 1st instruction of the test
|
|
; step to the WAI opcode, then manually tie the IRQ input low
|
|
; continue to step until you see the PC advance, then remove IRQ
|
|
; allow the routine to complete.
|
|
|
|
; WAI with interrupts disabled
|
|
ldx #$ff
|
|
txs
|
|
ldy #3
|
|
lda #0 ;IRQ not expected
|
|
sta I_src
|
|
set_stat intdis
|
|
wai
|
|
dey
|
|
dey
|
|
dey
|
|
trap_ne ;skipped opcodes!
|
|
|
|
success
|
|
|
|
; WAI with interrupts enabled
|
|
ldx #$ff
|
|
txs
|
|
ldy #7
|
|
lda #2 ;IRQ expected
|
|
sta I_src
|
|
set_stat 0
|
|
wai
|
|
dey
|
|
dey
|
|
dey
|
|
lda I_src
|
|
trap_ne ;IRQ vector not called
|
|
dey
|
|
trap_ne ;skipped opcodes!
|
|
|
|
success
|
|
|
|
; manual test for the STP opcode of the 65c02
|
|
|
|
stp macro
|
|
db $db ;STP opcode
|
|
endm
|
|
|
|
; set PC to the 1st instruction of the test, then run
|
|
nop
|
|
nop
|
|
stp ;expected end of operation
|
|
nop
|
|
nop
|
|
trap ;overran STP
|
|
|
|
;end of manual tests
|
|
|
|
;---------------------------------------------------------------------------
|
|
;trap in case of unexpected IRQ, NMI, BRK, RESET - IRQ, NMI, BRK test target
|
|
dey
|
|
dey
|
|
nmi_trap
|
|
if NMI_bit < 0
|
|
dey
|
|
dey
|
|
dey
|
|
trap ;unexpected NMI
|
|
else
|
|
php ;either SP or Y count will fail, if we do not hit
|
|
dey
|
|
dey
|
|
dey
|
|
sta nmi_a ;save regsters during NMI
|
|
stx nmi_x
|
|
pla
|
|
pha
|
|
sta nmi_f
|
|
lda I_src ;NMI expected?
|
|
and #4
|
|
trap_eq ;unexpexted NMI - check stack for conditions
|
|
pla ;test I-flag was set
|
|
pha
|
|
and #intdis
|
|
trap_eq ;I-flag not set
|
|
pla ;return with other flags reversed
|
|
eor #m8-fai-decmode
|
|
pha
|
|
tsx
|
|
lda $102,x ;test break on stack
|
|
and #break
|
|
trap_ne ;unexpected B-flag! - this may fail on a real 6502
|
|
;due to a hardware bug on concurrent BRK & NMI
|
|
lda I_src ;mark expected NMI has occured
|
|
and #$ff-4
|
|
sta I_src
|
|
I_clr NMI_bit
|
|
ldx nmi_x
|
|
inx
|
|
stx nmi_count
|
|
lda #'I' ;mark (NM)I
|
|
plp ;should be reversed by rti
|
|
rti
|
|
endif
|
|
|
|
res_trap
|
|
trap ;unexpected RESET
|
|
|
|
dey
|
|
dey
|
|
irq_trap ;BRK & IRQ test
|
|
php ;either SP or Y count will fail, if we do not hit
|
|
dey
|
|
dey
|
|
dey
|
|
sta irq_a ;save registers during IRQ/BRK
|
|
stx irq_x
|
|
pla
|
|
pha
|
|
sta irq_f
|
|
lda I_src ;IRQ expected?
|
|
and #3
|
|
trap_eq ;unexpexted IRQ/BRK - check stack for conditions
|
|
pla ;test I-flag was set
|
|
pha
|
|
and #intdis
|
|
trap_eq ;I-flag not set
|
|
pla ;return with other flags reversed
|
|
eor #m8-fai-decmode
|
|
pha
|
|
tsx
|
|
lda $102,x ;test break on stack
|
|
and #break
|
|
bne brk_trap
|
|
|
|
lda I_src ;IRQ expected?
|
|
and #2
|
|
trap_eq ;unexpexted IRQ - check stack for conditions
|
|
lda I_src ;mark expected IRQ has occured
|
|
and #$ff-2
|
|
sta I_src
|
|
I_clr IRQ_bit
|
|
ldx irq_x
|
|
inx
|
|
stx irq_count
|
|
lda #'Q' ;mark (IR)Q
|
|
plp ;should be reversed by rti
|
|
rti
|
|
|
|
brk_trap
|
|
lda I_src ;break expected?
|
|
and #1
|
|
trap_eq ;unexpected BRK - check stack for conditions
|
|
lda I_src ;mark expected BRK has occured
|
|
and #$ff-1
|
|
sta I_src
|
|
ldx irq_x
|
|
inx
|
|
stx brk_count
|
|
lda irq_a
|
|
lda #'K' ;mark (BR)K
|
|
plp ;should be reversed by rti
|
|
rti
|
|
|
|
if report = 1
|
|
rep_int = 1
|
|
include "report.i65"
|
|
endif
|
|
|
|
|
|
;system vectors
|
|
if (load_data_direct = 1)
|
|
org $fffa
|
|
dw nmi_trap
|
|
dw res_trap
|
|
dw irq_trap
|
|
else
|
|
vec_init
|
|
vec_bss equ $fffa
|
|
dw nmi_trap
|
|
dw res_trap
|
|
dw irq_trap
|
|
endif
|
|
|
|
end start
|
|
|
|
|