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Disregard operand address, part 2 (of 2)

Browse Source 
Added assembler regression tests, for 6502 and 65816.

The "remove formatting" action now clears the flag.  It's a bit of a
stretch to call it "formatting" but this feels right.

Updated the documentation, adding a new section about embedded
instructions to the intro material.
This commit is contained in:
Andy McFadden
2025-07-30 15:37:30 -07:00
parent ec50f48f95
commit cae1fa5173
21 changed files with 901 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
SourceGen/MainController.cs
+13 -2
View File
@@ -3561,6 +3561,9 @@ namespace SourceGen {
}
public void RemoveFormatting() {
const DisasmProject.MiscFlag clearMask =
(DisasmProject.MiscFlag.DisregardOperandAddress);
RangeSet sel = OffsetSetFromSelected();
ChangeSet cs = new ChangeSet(16);
foreach (int offset in sel) {
@@ -3572,8 +3575,8 @@ namespace SourceGen {
// Formatted?
if (mProject.OperandFormats.TryGetValue(offset, out FormatDescriptor oldFd)) {
Debug.WriteLine("Remove format from +" + offset.ToString("x6"));
UndoableChange uc = UndoableChange.CreateOperandFormatChange(offset,
oldFd, null);
UndoableChange uc =
UndoableChange.CreateOperandFormatChange(offset, oldFd, null);
cs.Add(uc);
}
@@ -3587,6 +3590,14 @@ namespace SourceGen {
UndoableChange uc = UndoableChange.CreateLabelChange(offset, attr.Symbol, null);
cs.Add(uc);
}
DisasmProject.MiscFlag curFlags = mProject.MiscFlags[offset];
if ((curFlags & clearMask) != 0) {
DisasmProject.MiscFlag newFlags = mProject.MiscFlags[offset] & ~clearMask;
UndoableChange uc =
UndoableChange.CreateMiscFlagsChange(offset, curFlags, newFlags);
cs.Add(uc);
}
}
if (cs.Count != 0) {
SourceGen/SGTestData/20310-disregard-operand
BIN
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SourceGen/SGTestData/20310-disregard-operand.dis65
+111
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@@ -0,0 +1,111 @@
### 6502bench SourceGen dis65 v1.0 ###
{
"_ContentVersion":7,
"FileDataLength":768,
"FileDataCrc32":-195338794,
"ProjectProps":{
"CpuName":"6502",
"IncludeUndocumentedInstr":false,
"TwoByteBrk":false,
"EntryFlags":32702671,
"AutoLabelStyle":"Simple",
"AnalysisParams":{
"AnalyzeUncategorizedData":true,
"DefaultTextScanMode":"LowHighAscii",
"MinCharsForString":4,
"SeekNearbyTargets":false,
"UseRelocData":false,
"SmartPlpHandling":false,
"SmartPlbHandling":true},
"PlatformSymbolFileIdentifiers":[],
"ExtensionScriptFileIdentifiers":[],
"ProjectSyms":{
}},
"AddressMap":[{
"Offset":0,
"Addr":11008,
"Length":768,
"PreLabel":"",
"DisallowInward":false,
"DisallowOutward":false,
"IsRelative":false}],
"TypeHints":[{
"Low":0,
"High":0,
"Hint":"Code"}],
"StatusFlagOverrides":{
},
"MiscFlags":{
"262":1,
"271":1,
"279":1,
"280":1,
"281":1,
"282":1,
"283":1,
"290":1,
"292":1,
"300":1,
"304":1},
"Comments":{
},
"LongComments":{
},
"Notes":{
},
"UserLabels":{
"300":{
"Label":"site4a",
"Value":11308,
"Source":"User",
"Type":"GlobalAddr",
"LabelAnno":"None"},
"304":{
"Label":"site4b",
"Value":11312,
"Source":"User",
"Type":"GlobalAddr",
"LabelAnno":"None"}},
"OperandFormats":{
"300":{
"Length":3,
"Format":"NumericLE",
"SubFormat":"Symbol",
"SymbolRef":{
"Label":"site4b",
"Part":"Low"},
"Extra":null},
"304":{
"Length":3,
"Format":"NumericLE",
"SubFormat":"Symbol",
"SymbolRef":{
"Label":"site4a",
"Part":"Low"},
"Extra":null}},
"LvTables":{
},
"Visualizations":[],
"VisualizationAnimations":[],
"VisualizationSets":{
},
"RelocList":{
},
"DbrValues":{
}}
SourceGen/SGTestData/20312-disregard-operand
BIN
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SourceGen/SGTestData/20312-disregard-operand.dis65
+109
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@@ -0,0 +1,109 @@
### 6502bench SourceGen dis65 v1.0 ###
{
"_ContentVersion":7,
"FileDataLength":769,
"FileDataCrc32":-263728457,
"ProjectProps":{
"CpuName":"65816",
"IncludeUndocumentedInstr":false,
"TwoByteBrk":false,
"EntryFlags":32702671,
"AutoLabelStyle":"Simple",
"AnalysisParams":{
"AnalyzeUncategorizedData":true,
"DefaultTextScanMode":"LowHighAscii",
"MinCharsForString":4,
"SeekNearbyTargets":false,
"UseRelocData":false,
"SmartPlpHandling":false,
"SmartPlbHandling":true},
"PlatformSymbolFileIdentifiers":[],
"ExtensionScriptFileIdentifiers":[],
"ProjectSyms":{
"badness":{
"DataDescriptor":{
"Length":1,
"Format":"NumericLE",
"SubFormat":"Hex",
"SymbolRef":null,
"Extra":null},
"Comment":"",
"HasWidth":false,
"Direction":"ReadWrite",
"MultiMask":null,
"Label":"badness",
"Value":11513775,
"Source":"Project",
"Type":"ExternalAddr",
"LabelAnno":"None"}}},
"AddressMap":[{
"Offset":0,
"Addr":76544,
"Length":513,
"PreLabel":"",
"DisallowInward":false,
"DisallowOutward":false,
"IsRelative":false},
{
"Offset":513,
"Addr":142336,
"Length":256,
"PreLabel":"",
"DisallowInward":false,
"DisallowOutward":false,
"IsRelative":false}],
"TypeHints":[{
"Low":0,
"High":0,
"Hint":"Code"}],
"StatusFlagOverrides":{
},
"MiscFlags":{
"260":1,
"264":1,
"513":1,
"514":1,
"515":1,
"516":1,
"517":1,
"518":1,
"519":1},
"Comments":{
},
"LongComments":{
},
"Notes":{
},
"UserLabels":{
},
"OperandFormats":{
"514":{
"Length":4,
"Format":"NumericLE",
"SubFormat":"Decimal",
"SymbolRef":null,
"Extra":null}},
"LvTables":{
},
"Visualizations":[],
"VisualizationAnimations":[],
"VisualizationSets":{
},
"RelocList":{
},
"DbrValues":{
}}
SourceGen/SGTestData/Expected/20310-disregard-operand_64tass.S
+71
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@@ -0,0 +1,71 @@
.cpu "6502"
* = $2b00
jsr L2C00
jsr L2C05
jsr L2C07
jsr L2C0D
jsr L2C10
jsr L2C17
jsr L2C18
jsr L2C19
jsr L2C1A
jsr L2C1F
jsr L2C23
jsr site4a
jsr site4b
jmp L2D00
.fill 214,$2b
L2C00 bit $ff58
bvs L2C0C
L2C05 sec
.byte $90
L2C07 clc
clv
bvc L2C0C
.byte $80
L2C0C rts
L2C0D lda #$00
.byte $2c
L2C10 lda #$ff
sta _L2C16
rts
_L2C16 .byte $cc
L2C17 .byte $2c
L2C18 .byte $2c
L2C19 .byte $2c
L2C1A .byte $2c
.byte $2c
nop
nop
rts
L2C1F lda #$1f
sec
.byte $90
L2C23 .byte $a9
.byte $f0
clc
nop
bcc _L2C2A
asl a
_L2C2A nop
rts
site4a lda site4b+1
rts
site4b lda site4a
rts
.fill 204,$2c
L2D00 rts
.fill 255,$2d
SourceGen/SGTestData/Expected/20310-disregard-operand_acme.S
+71
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@@ -0,0 +1,71 @@
!cpu 6502
* = $2b00
jsr L2C00
jsr L2C05
jsr L2C07
jsr L2C0D
jsr L2C10
jsr L2C17
jsr L2C18
jsr L2C19
jsr L2C1A
jsr L2C1F
jsr L2C23
jsr site4a
jsr site4b
jmp L2D00
!fill 214,$2b
L2C00 bit $ff58
bvs L2C0C
L2C05 sec
!byte $90
L2C07 clc
clv
bvc L2C0C
!byte $80
L2C0C rts
L2C0D lda #$00
!byte $2c
L2C10 lda #$ff
sta @L2C16
rts
@L2C16 !byte $cc
L2C17 !byte $2c
L2C18 !byte $2c
L2C19 !byte $2c
L2C1A !byte $2c
!byte $2c
nop
nop
rts
L2C1F lda #$1f
sec
!byte $90
L2C23 !byte $a9
!byte $f0
clc
nop
bcc @L2C2A
asl
@L2C2A nop
rts
site4a lda site4b+1
rts
site4b lda site4a
rts
!fill 204,$2c
L2D00 rts
!fill 255,$2d
SourceGen/SGTestData/Expected/20310-disregard-operand_cc65.S
+71
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@@ -0,0 +1,71 @@
.setcpu "6502"
.org $2b00
jsr L2C00
jsr L2C05
jsr L2C07
jsr L2C0D
jsr L2C10
jsr L2C17
jsr L2C18
jsr L2C19
jsr L2C1A
jsr L2C1F
jsr L2C23
jsr site4a
jsr site4b
jmp L2D00
.res 214,$2b
L2C00: bit $ff58
bvs L2C0C
L2C05: sec
.byte $90
L2C07: clc
clv
bvc L2C0C
.byte $80
L2C0C: rts
L2C0D: lda #$00
.byte $2c
L2C10: lda #$ff
sta @L2C16
rts
@L2C16: .byte $cc
L2C17: .byte $2c
L2C18: .byte $2c
L2C19: .byte $2c
L2C1A: .byte $2c
.byte $2c
nop
nop
rts
L2C1F: lda #$1f
sec
.byte $90
L2C23: .byte $a9
.byte $f0
clc
nop
bcc @L2C2A
asl A
@L2C2A: nop
rts
site4a: lda site4b+1
rts
site4b: lda site4a
rts
.res 204,$2c
L2D00: rts
.res 255,$2d
SourceGen/SGTestData/Expected/20310-disregard-operand_cc65.cfg
+9
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@@ -0,0 +1,9 @@
# 6502bench SourceGen generated linker script for 20310-disregard-operand
MEMORY {
MAIN: file=%O, start=%S, size=65536;
}
SEGMENTS {
CODE: load=MAIN, type=rw;
}
FEATURES {}
SYMBOLS {}
SourceGen/SGTestData/Expected/20310-disregard-operand_merlin32.S
+70
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@@ -0,0 +1,70 @@
org $2b00
jsr L2C00
jsr L2C05
jsr L2C07
jsr L2C0D
jsr L2C10
jsr L2C17
jsr L2C18
jsr L2C19
jsr L2C1A
jsr L2C1F
jsr L2C23
jsr site4a
jsr site4b
jmp L2D00
ds 214,$2b
L2C00 bit $ff58
bvs L2C0C
L2C05 sec
dfb $90
L2C07 clc
clv
bvc L2C0C
dfb $80
L2C0C rts
L2C0D lda #$00
dfb $2c
L2C10 lda #$ff
sta :L2C16
rts
:L2C16 dfb $cc
L2C17 dfb $2c
L2C18 dfb $2c
L2C19 dfb $2c
L2C1A dfb $2c
dfb $2c
nop
nop
rts
L2C1F lda #$1f
sec
dfb $90
L2C23 dfb $a9
dfb $f0
clc
nop
bcc :L2C2A
asl A
:L2C2A nop
rts
site4a lda site4b+1
rts
site4b lda site4a
rts
ds 204,$2c
L2D00 rts
ds 255,$2d
SourceGen/SGTestData/Expected/20312-disregard-operand_64tass.S
+45
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@@ -0,0 +1,45 @@
.cpu "65816"
.logical $012b00
.as
.xs
clc
xce
sep #$30
jsr L12C00
jsl L22C00
jsl L22C01
jsl L22C02
jsl L22C03
jsl L22C04
jmp L12D00
.fill 226,$2b
L12C00 lda #$02
pha
plb
lda $2c07
rts
.byte $ad
.byte $00
.fill 246,$2c
L12D00 rts
.here
.logical $022c00
L22C00 .byte $af
L22C01 .byte $af
L22C02 .byte $af
L22C03 .byte $af
L22C04 .byte $af
.byte $af
.byte $af
nop
nop
nop
rtl
.fill 245,$8c
.here
SourceGen/SGTestData/Expected/20312-disregard-operand_acme.S
+29
View File
@@ -0,0 +1,29 @@
;ACME can't handle 65816 code that lives outside bank zero
* = $0000
!pseudopc $012b00 {
!hex 18fbe23020002c22002c0222012c0222022c0222032c0222042c024c002d2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex 2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b2b
!hex a90248abad072c60ad002c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c2c
!hex 60afafafafafafafeaeaea6b8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c8c
!hex 8c
}
SourceGen/SGTestData/Expected/20312-disregard-operand_cc65.S
+43
View File
@@ -0,0 +1,43 @@
.setcpu "65816"
.org $012b00
.a8
.i8
clc
xce
sep #$30
jsr L12C00 & $ffff
jsl L22C00
jsl L22C01
jsl L22C02
jsl L22C03
jsl L22C04
jmp L12D00 & $ffff
.res 226,$2b
L12C00: lda #$02
pha
plb
lda $2c07
rts
.byte $ad
.byte $00
.res 246,$2c
L12D00: rts
.org $022c00
L22C00: .byte $af
L22C01: .byte $af
L22C02: .byte $af
L22C03: .byte $af
L22C04: .byte $af
.byte $af
.byte $af
nop
nop
nop
rtl
.res 245,$8c
SourceGen/SGTestData/Expected/20312-disregard-operand_cc65.cfg
+9
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@@ -0,0 +1,9 @@
# 6502bench SourceGen generated linker script for 20312-disregard-operand
MEMORY {
MAIN: file=%O, start=%S, size=65536;
}
SEGMENTS {
CODE: load=MAIN, type=rw;
}
FEATURES {}
SYMBOLS {}
SourceGen/SGTestData/Expected/20312-disregard-operand_merlin32.S
+40
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@@ -0,0 +1,40 @@
org $012b00
clc
xce
sep #$30
jsr L12C00
jsl L22C00
jsl L22C01
jsl L22C02
jsl L22C03
jsl L22C04
jmp L12D00
ds 226,$2b
L12C00 lda #$02
pha
plb
lda $2c07
rts
dfb $ad
dfb $00
ds 246,$2c
L12D00 rts
org $022c00
L22C00 dfb $af
L22C01 dfb $af
L22C02 dfb $af
L22C03 dfb $af
L22C04 dfb $af
dfb $af
dfb $af
nop
nop
nop
rtl
ds 245,$8c
SourceGen/SGTestData/Source/20310-disregard-operand.S
+83
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@@ -0,0 +1,83 @@
; Copyright 2025 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0).
;
; Tests the "disregard operand address" feature.
;
; Assembler: Merlin 32
;
org $2b00
; Reference all code entry points.
jsr site1a
jsr site1b
jsr site1c
jsr site2a
jsr site2b
jsr site3a
jsr site3b
jsr site3c
jsr site3d
jsr cmdd
jsr cmdb
jsr site4a
jsr site4b
jmp done
ds \,$2b ;pad to leave room for more
; Classic $C3xx entry
site1a bit $ff58 ;set V-flag
bvs later ;in actual ROM, always taken
site1b sec
dfb $90 ;BCC (never taken) <-- EDIT: disregard operand
site1c clc
clv
bvc later ;(always taken)
dfb $80
later rts
; Basic register config.
site2a lda #$00
dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
site2b lda #$ff
sta out
rts
out dfb $cc
; Multi-nested BIT instructions.
site3a dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
site3b dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
site3c dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
site3d dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
dfb $2c ;BIT (ignored) <-- EDIT: disregard operand
nop
nop
rts
; Piece of //c 16KB ROM ($ca79).
cmdd lda #$1f ;mask
sec ;C=1 means high 3 bits
dfb $90 ;BCC (never taken) <-- EDIT: disregard operand (and below)
cmdb lda #$f0 ;mask lower 4 bits; also BEQ instruction (never taken)
clc ;F0 will skip this if cmdd
nop
bcc noshift
asl A
noshift nop
rts
site4a lda site4b+1 ;EDIT: disregard operand, set operand to symbol
rts
site4b lda site4a ;EDIT: disregard operand, set operand to symbol
rts
ds \,$2c ;pad to leave room for more
done rts
ds \,$2d ;pad to ensure branches land internally
SourceGen/SGTestData/Source/20312-disregard-operand.S
+56
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@@ -0,0 +1,56 @@
; Copyright 2025 faddenSoft. All Rights Reserved.
; See the LICENSE.txt file for distribution terms (Apache 2.0).
;
; Tests the "disregard operand address" feature.
;
; Assembler: Merlin 32
;
org $012b00
clc
xce
sep #$30
mx %11
jsr st1_1a
jsl st2_1a
jsl st2_1b
jsl st2_1c
jsl st2_1d
jsl st2_1e
jmp done
ds \,$2b
st1_1a lda #$02
pha
plb
lda st1x ;EDIT: disregard operand
st1x rts
lda st1_1a ;EDIT: disregard operand, then remove code entry tag
ds \,$2c
done rts
;EDIT: create a project symbol $AFAFAF
org $022c00
st2_1a dfb $af ;EDIT: disregard operand (here and below)
st2_1b dfb $af ;EDIT: also format this one as decimal
st2_1c dfb $af
st2_1d dfb $af
st2_1e dfb $af
dfb $af
dfb $af
nop
nop
nop
rtl
ds \,$8c
docs/sgmanual/editors.html
+6
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@@ -124,6 +124,7 @@ be imported by other projects (see
<h2 id="instruction-operand">Edit Operand (Instruction)</h2>
<p>Operands can be formatted explicitly, or you can let the disassembler
select the format for you. By default, immediate constants and
addresses with no matching symbol are formatted as hex. Symbols
@@ -164,6 +165,11 @@ in a future release.)</p>
also have two operands: a direct page address, and a relative branch.
In general the direct page address is ignored, so these are treated as
branch instructions.</p>
<p>The <samp>Disregard Operand Address</samp> checkbox tells the code
analyzer to ignore the operand when scanning the code and creating labels.
This is useful in a few very specific situations, such as when instructions
embedded inside other instructions cause "dummy" address references, or when
inter-bank references in multi-bank ROM images don't resolve correctly.</p>
<p>The bottom part of the window has some shortcuts for working with
address references and local variables. These are primarily used to
docs/sgmanual/index.html
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@@ -66,6 +66,7 @@ using the <samp>Help &gt; Help</samp> menu item or by hitting
<ul>
<li><a href="intro-details.html#scripts">Extension Scripts</a></li>
</ul></li>
<li><a href="intro-details.html#embedded-instructions">Handling Embedded Instructions</a></li>
<li><a href="intro-details.html#pseudo-ops">Data and Directive Pseudo-Opcodes</a></li>
</ul></li>
docs/sgmanual/intro-details.html
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@@ -924,6 +924,68 @@ is launched, but may be manually deleted without harm.</p>
<a href="advanced.html#extension-scripts">advanced topics</a> section.</p>
<h2 id="embedded-instructions">Handling Embedded Instructions</h2>
<p>Sometimes code will cleverly embed instructions inside other instructions.
For example, suppose you have two entry points to a routine, and the only
difference is the state of the carry flag.</p>
<pre>
ENTRY1 SEC
.DD1 $90 ;BCC opcode, branch never taken
ENTRY2 CLC
[ ... ]
</pre>
<p>Calling ENTRY1 sets the carry and skips the CLC, which is embedded
in the BCC instruction. Calling ENTRY2 clears the carry.</p>
<p>When this is disassembled, all paths are shown, but the BCC line has
a downward triangle, and the "bytes" column is partially filled.</p>
<pre>
c305: 38 ENTRY1 sec
c306: 90 bcc &#x25bc; LC320
c307: 18 ENTRY2 clc
</pre>
<p>The BCC appears to branch to $C320. Even though the branch is never
taken when the code is executed, the disassembler will create a label at
the target address, and generate an entry in the cross-reference table.
(The disassembler knows that the branch is never taken and doesn't try to
follow it to execute code there, but for various reasons it's often useful
to treat it as a valid address reference anyway.) When the target address
is in an awkward place, such as the middle of a data item or instruction,
this can be disruptive.</p>
<p>This problem can be remedied by editing the operand of the BCC
instruction and checking the "disregard operand address" box. The
operand will be formatted as a plain hex value instead.</p>
<p>Another common example:</p>
<pre>
ENTRY1 LDA #$01
.DD1 $2C ;BIT opcode, result ignored
ENTRY2 LDA #$FF
[...]
</pre>
<p>This turns into:</p>
<pre>
2c0d: a9 00 L2C0D lda #$01
2c0f: 2c bit ▼ $ffa9
2c10: a9 ff L2C10 lda #$ff
</pre>
<p>In this case, the BIT instruction performs an operation whose result
is ignored. So long as accesses to address $FFA9 don't have any side-effects,
this works fine. We don't want the disassembly to generate a label or look
for a matching project symbol, though, so the BIT instruction should also
have the "disregard operand address" box checked.</p>
<p>It should be noted that disregarding the operand does not prevent you
from formatting it. You can even format it as a symbol by specifying one
in the operand editor.</p>
<h2 id="pseudo-ops">Data and Directive Pseudo-Opcodes</h2>
<p>The on-screen code list shows assembler directives that are similar
docs/sgmanual/mainwin.html
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@@ -684,9 +684,9 @@ what splits a region), or is the last byte in the file.</p>
This removes the visible formatting as well as any formatting instructions
that got embedded inside multi-byte data items. (You will be notified of
such things in the <a href="#messages">message list</a>.)</p>
<p>This will also remove any labels that are embedded in multi-byte items,
without removing visible labels.</p>
without removing visible labels, and will clear the "disregard operand
address" flag.</p>
<h3 id="toggle-data">Toggle Data Scan</h3>