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125 lines
2.4 KiB
Coq
125 lines
2.4 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (clk);
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input clk;
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reg [0:0] d1;
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reg [2:0] d3;
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reg [7:0] d8;
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wire [0:0] q1;
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wire [2:0] q3;
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wire [7:0] q8;
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// verilator lint_off UNOPTFLAT
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reg ena;
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// verilator lint_on UNOPTFLAT
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condff #(12) condff
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(.clk(clk), .sen(1'b0), .ena(ena),
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.d({d8,d3,d1}),
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.q({q8,q3,q1}));
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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//$write("%x %x %x %x\n", cyc, q8, q3, q1);
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cyc <= cyc + 1;
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if (cyc==1) begin
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d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
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ena <= 1'b1;
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end
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if (cyc==2) begin
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d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
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ena <= 1'b0;
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end
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if (cyc==3) begin
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d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
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ena <= 1'b1;
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if (q8 != 8'h11) $stop;
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end
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if (cyc==4) begin
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d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
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ena <= 1'b1;
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if (q8 != 8'h11) $stop;
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end
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if (cyc==5) begin
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d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
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ena <= 1'b1;
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if (q8 != 8'h44) $stop;
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end
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if (cyc==6) begin
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if (q8 != 8'h77) $stop;
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end
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if (cyc==7) begin
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if (q8 != 8'h88) $stop;
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end
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//
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if (cyc==20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module condff (clk, sen, ena, d, q);
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parameter WIDTH = 1;
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input clk;
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input sen;
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input ena;
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input [WIDTH-1:0] d;
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output [WIDTH-1:0] q;
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condffimp #(.WIDTH(WIDTH))
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imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
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endmodule
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module condffimp (clk, sen, ena, d, q);
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parameter WIDTH = 1;
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input clk;
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input sen;
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input ena;
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input [WIDTH-1:0] d;
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output reg [WIDTH-1:0] q;
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wire gatedclk;
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clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
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always @(posedge gatedclk) begin
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if (gatedclk === 1'bX) begin
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q <= {WIDTH{1'bX}};
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end
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else begin
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q <= d;
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end
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end
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endmodule
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module clockgate (clk, sen, ena, gatedclk);
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input clk;
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input sen;
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input ena;
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output gatedclk;
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reg ena_b;
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wire gatedclk = clk & ena_b;
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// verilator lint_off COMBDLY
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always @(clk or ena or sen) begin
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if (~clk) begin
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ena_b <= ena | sen;
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end
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else begin
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if ((clk^sen)===1'bX) ena_b <= 1'bX;
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end
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end
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// verilator lint_on COMBDLY
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endmodule
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