more verilog updates

demo.html

@@ -92,13 +92,14 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
           </p>
        </div>
        <div class="col-md-4">
+       <!--
          <h2><a href="redir.html?platform=apple2">Apple ][+</a></h2>
          <p>
          You can even write C or 6502 assembler code for Woz's creation, the
          <a href="redir.html?platform=apple2">Apple ][+</a>.
          Thrill to the unusual frame buffer layout and one-bit speaker output!
          <img class="img-responsive" src="//upload.wikimedia.org/wikipedia/commons/thumb/6/68/Apple_II_Plus.jpg/512px-Apple_II_Plus.jpg">
-         <!--
+         -->
           <h2><a href="redir.html?platform=verilog">Hardware Design</a></h2>
           <p>
           Software not enough for you?
@@ -112,7 +113,6 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
           and connect to a legacy CRT or TV.
           </p>
           <img class="img-responsive" src="images/fpga.jpg">
-          -->
         </div>
       </div>
 
@@ -144,16 +144,15 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
         </div>
       </div>
     </div>
-<!--
     <div class="container">
       <div class="row">
         <div class="col-md-2">
-        <a target="_blank"  href="https://www.amazon.com/gp/product/1541021304/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=1541021304&linkCode=as2&tag=pzp-20&linkId=c149f6365c0a676065eb6d7c5f8dd6ae" onclick="ga('send', 'event', 'books', 'click', 'verilog');">
+        <a target="_blank"  href="https://www.amazon.com/gp/product/B07LD48CTV/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=B07LD48CTV&linkCode=as2&tag=pzp-20&linkId=c149f6365c0a676065eb6d7c5f8dd6ae" onclick="ga('send', 'event', 'books', 'click', 'verilog');">
 <img class="img-responsive" border="0" src="./images/book_verilog.jpg" ></a>
-<img src="//ir-na.amazon-adsystem.com/e/ir?t=pzp-20&l=am2&o=1&a=1541021304" />
+<img src="//ir-na.amazon-adsystem.com/e/ir?t=pzp-20&l=am2&o=1&a=B07LD48CTV" />
         </div>
         <div class="col-md-4">
-        <a target="_blank"  href="https://www.amazon.com/gp/product/1541021304/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=1541021304&linkCode=as2&tag=pzp-20&linkId=c149f6365c0a676065eb6d7c5f8dd6ae" onclick="ga('send', 'event', 'books', 'click', 'verilog');">
+        <a target="_blank"  href="https://www.amazon.com/gp/product/B07LD48CTV/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=B07LD48CTV&linkCode=as2&tag=pzp-20&linkId=c149f6365c0a676065eb6d7c5f8dd6ae" onclick="ga('send', 'event', 'books', 'click', 'verilog');">
           <h3>Designing Video Game Hardware in Verilog</h3>
         </a>
         <p>
@@ -164,7 +163,6 @@ At the end of this adventure, you should be well-equipped to begin exploring the
         </div>
       </div>
     </div>
--->
 
     <h1 class="text-center">Supported Platforms</h1>
     <div class="container">

index.html

@@ -118,14 +118,12 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
                <li><a class="dropdown-item" href="?platform=sound_williams-z80" id="item_platform_sound_williams_z80">Williams Sound (Z80)</a></li>
              </ul>
           </li>
-          <!--
           <li class="dropdown dropdown-submenu">
              <a tabindex="-1" href="#">Hardware</a>
              <ul class="dropdown-menu">
                <li><a class="dropdown-item" href="?platform=verilog" id="item_platform_verilog">Verilog</a></li>
              </ul>
           </li>
-          -->
           <li class="dropdown dropdown-submenu">
              <a tabindex="-1" href="#">Other</a>
              <ul class="dropdown-menu">
@@ -187,12 +185,10 @@ if (window.location.host.endsWith('8bitworkshop.com')) {
           <img src="images/book_arcade.png"/>
           &nbsp;&nbsp;<b>Making 8-bit Arcade Games in C</b><!-- (Print Edition)-->
         </a>
-        <!--
-        <a class="dropdown-item dropdown-link" target="_book_arcade_pdf" href="https://gumroad.com/l/8bitworkshoparcadebook">
-          <img src="images/book_arcade.png"/>
-          &nbsp;&nbsp;<b>Making 8-bit Arcade Games in C</b> (Downloadable PDF)
+        <a class="dropdown-item dropdown-link" target="_book_verilog" href="https://www.amazon.com/gp/product/B07LD48CTV/ref=as_li_tl?ie=UTF8&camp=1789&creative=9325&creativeASIN=B07LD48CTV&linkCode=as2&tag=pzp-20">
+          <img src="images/book_verilog.png"/>
+          &nbsp;&nbsp;<b>Designing Video Game Hardware in Verilog</b>
         </a>
-        -->
       </li>
     </ul>
   </span>

presets/verilog/binary_counter.v

@@ -0,0 +1,50 @@
+
+/*
+A clock divider in Verilog, using both the cascading
+flip-flop method and the binary counter method.
+*/
+
+module clock_divider(
+  input clk,
+  input reset,
+  output reg clk_div2,
+  output reg clk_div4,
+  output reg clk_div8,
+  output reg clk_div16,
+  output reg [3:0] counter,
+  output cntr_div2,
+  output cntr_div4,
+  output cntr_div8,
+  output cntr_div16
+);
+
+  // simple ripple clock divider
+  
+  always @(posedge clk)
+    clk_div2 <= ~clk_div2;
+
+  always @(posedge clk_div2)
+    clk_div4 <= ~clk_div4;
+
+  always @(posedge clk_div4)
+    clk_div8 <= ~clk_div8;
+
+  always @(posedge clk_div8)
+    clk_div16 <= ~clk_div16;
+
+  // use bits of (4-bit) counter to divide clocks
+  
+  always @(posedge clk or posedge reset)
+  begin
+    if (reset)
+      counter <= 0;
+    else
+      counter <= counter + 1;
+  end
+
+  assign cntr_div2 = counter[0];
+  assign cntr_div4 = counter[1];
+  assign cntr_div8 = counter[2];
+  assign cntr_div16 = counter[3];
+
+endmodule

presets/verilog/clock_divider.v

@@ -1,7 +1,7 @@
 
 /*
-A clock divider in Verilog, using both the cascading
-flip-flop method and the counter method.
+A clock divider in Verilog, using the cascading
+flip-flop method.
 */
 
 module clock_divider(
@@ -10,12 +10,7 @@ module clock_divider(
   output reg clk_div2,
   output reg clk_div4,
   output reg clk_div8,
-  output reg clk_div16,
-  output reg [3:0] counter,
-  output cntr_div2,
-  output cntr_div4,
-  output cntr_div8,
-  output cntr_div16
+  output reg clk_div16
 );
 
   // simple ripple clock divider
@@ -32,17 +27,4 @@ module clock_divider(
   always @(posedge clk_div8)
     clk_div16 <= ~clk_div16;
 
-  // use bits of (4-bit) counter to divide clocks
-  
-  always @(posedge clk or posedge reset)
-    if (reset)
-      counter <= 0;
-    else
-      counter <= counter + 1;
-
-  assign cntr_div2 = counter[0];
-  assign cntr_div4 = counter[1];
-  assign cntr_div8 = counter[2];
-  assign cntr_div16 = counter[3];
-
 endmodule

src/platform/verilog.ts

@@ -10,6 +10,7 @@ declare var Split;
 
 var VERILOG_PRESETS = [
   {id:'clock_divider.v', name:'Clock Divider'},
+  {id:'binary_counter.v', name:'Binary Counter'},
   {id:'hvsync_generator.v', name:'Video Sync Generator'},
   {id:'test_hvsync.v', name:'Test Pattern'},
   {id:'7segment.v', name:'7-Segment Decoder'},