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verilog preset update
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@ -84,6 +84,7 @@ TODO:
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- wasm dynamic linking of emulators (https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md)
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- use alternate confirm/prompt dialogs
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- https://github.com/jvilk/BrowserFS
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- verilog: in .asm file editing .v files doesnt update
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WEB WORKER FORMAT
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@ -58,8 +58,9 @@ module tile_renderer(clk, reset, hpos, vpos,
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case (hpos)
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// assert busy 5 cycles before first RAM read
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HLOAD-8: ram_busy <= 1;
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// read page base for row
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// set address for row in page base table
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HLOAD-3: ram_addr <= {page_base, 3'b000, row};
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// read row_base from page table (2 bytes)
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HLOAD-1: row_base <= ram_read;
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// deassert BUSY and increment row counter
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HLOAD+34: begin
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@ -70,18 +71,23 @@ module tile_renderer(clk, reset, hpos, vpos,
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// load row of tile data from RAM
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// (last two twice)
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if (hpos >= HLOAD && hpos < HLOAD+34) begin
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// set address bus to (row_base + hpos)
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ram_addr <= row_base + 16'(hpos[4:0]);
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row_buffer[hpos[4:0] - 5'd2] <= ram_read;
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// store value on data bus from (row_base + hpos - 2)
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// which was read two cycles ago
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row_buffer[hpos[4:0] - 2] <= ram_read;
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end
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end
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// latch character data
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if (hpos < 256) begin
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case (hpos[2:0])
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7: begin
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// read next cell
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cur_cell <= row_buffer[col+1];
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end
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endcase
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end else if (hpos == 308) begin
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// read first cell of next row
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cur_cell <= row_buffer[0];
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end
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end
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@ -152,6 +158,7 @@ module test_tilerender_top(clk, reset, hsync, vsync, rgb);
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.data(rom_data)
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);
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// draw border around edges of tile map
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initial begin
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for (int i=0; i<32; i++) begin
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ram.mem[16'h7e00 + 16'(i)] = 16'(i*32);
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2
tss
2
tss
@ -1 +1 @@
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Subproject commit 61a1691a1de05dca3b694bf603db49ffbaf572cf
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Subproject commit d630ddcb29d74a178cde043d74188fac35d6a21f
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