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verilog: parse warnings as warnings
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@@ -12,6 +12,7 @@ See [extension/CHANGELOG.md](extension/CHANGELOG.md).
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- Platform detection no longer confuses the Atari 8-bit targets: `atari.h` means the 800 (it is guarded by `__ATARI__`), `atari5200.h` means the 5200, and a folder named for a platform breaks a near-tie.
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- Emulators now run on a timeline: step back, seek, reverse run, `rbreak`, and deterministic replay with a replay-verification test that found determinism bugs in several platforms.
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- Step Over for C and assembly sources, a Breakpoints pane, and more breakpoint conditions.
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- Verilator warnings (width mismatches, etc.) no longer fail the build and show as warnings; a Verilator error no longer also reports "tool called exit(1)".
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- Call Stack view renamed Call Graph, with clocks and more detail per line.
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- Compiler warnings no longer fail a build or get lost: `WorkerError` has an optional `severity`, and a successful build returns `warnings`. cc65/ca65/ld65 and SDCC warnings show as gutter markers in the IDE (not in the error dialog), as warnings in the VS Code Problems panel, and on stderr from `8bws` (`--no-warnings` hides them). SDCC 3 warnings no longer fail the build.
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- `buildpresets` lists compiler warnings per preset, flags a rising warning count against `--baseline`, and fails builds with warnings unless `--no-strict` is given.
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@@ -6,7 +6,7 @@ import { Assembler } from "../assembler";
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import * as vxmlparser from '../../common/hdl/vxmlparser';
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import { EmscriptenModule, emglobal, execMain, getWASMMemory, loadNative, moduleInstFn, print_fn, setupFS } from "../wasmutils";
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import { getWorkFileAsString, BuildStep, BuildStepResult, gatherFiles, staleFiles, populateFiles, starttime, endtime, putWorkFile, anyTargetChanged, populateExtraFiles } from "../builder";
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import { makeErrorMatcher } from "../listingutils";
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import { makeErrorMatcher, hasErrors } from "../listingutils";
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function detectModuleName(code: string) {
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var m = /^\s*module\s+(\w+_top)\b/m.exec(code)
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@@ -128,7 +128,13 @@ export function compileVerilator(step: BuildStep): BuildStepResult {
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if (staleFiles(step, [xmlPath])) {
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// TODO: %Error: Specified --top-module 'ALU' isn't at the top level, it's under another cell 'cpu'
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// TODO: ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
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var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?):(\d+)?[:]?\s*(.+)/i, 3, 4, step.path, 2);
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var match_errs = makeErrorMatcher(errors, /%(.+?): (.+?):(\d+)?[:]?\s*(.+)/i, 3, 4, step.path, 2);
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// verilator prefixes warnings with "%Warning-<TYPE>:"
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var match_fn = (s: string) => {
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var n = errors.length;
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match_errs(s);
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if (errors.length > n && /^%Warning/.test(s)) errors[n].severity = 'warning';
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};
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var verilator_mod: EmscriptenModule = emglobal.verilator_bin({
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instantiateWasm: moduleInstFn('verilator_bin'),
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noInitialRun: true,
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@@ -162,20 +168,23 @@ export function compileVerilator(step: BuildStep): BuildStepResult {
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var args = ["--cc", "-O3",
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"-DEXT_INLINE_ASM", "-DTOPMOD__" + topmod, "-D__8BITWORKSHOP__",
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"-Wall",
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"-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",
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"-Wno-fatal", "-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",
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"--x-assign", "fast", "--noassert", "--pins-sc-biguint",
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"--debug-check", // for XML output
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"--top-module", topmod, step.path]
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execMain(step, verilator_mod, args);
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} catch (e) {
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console.log(e);
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errors.push({ line: 0, msg: "Compiler internal error: " + e });
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// exit(1) is just the symptom if verilator already reported errors
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if (!hasErrors(errors)) {
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errors.push({ line: 0, msg: "Compiler internal error: " + e });
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}
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}
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endtime("compile");
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// remove boring errors
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errors = errors.filter(function (e) { return !/Exiting due to \d+/.exec(e.msg); }, errors);
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errors = errors.filter(function (e) { return !/Use ["][/][*]/.exec(e.msg); }, errors);
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if (errors.length) {
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if (hasErrors(errors)) {
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return { errors: errors };
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}
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starttime();
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@@ -203,7 +212,7 @@ export function compileVerilator(step: BuildStep): BuildStepResult {
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}
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return {
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output: xmlParser,
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errors: errors,
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warnings: errors,
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listings: listings,
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};
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}
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@@ -192,6 +192,13 @@ describe('Worker', function() {
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assert.ok(msg.warnings.length >= 1);
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assert.ok(msg.warnings.every(w => w.severity == 'warning' && w.line > 0));
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});
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it('should return Verilator warnings on a successful build, marked as warnings', async function() {
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var msg = await queryWorker({code:"module t_top(input clk, output reg [3:0] q);\n always @(posedge clk) q <= 5'd300;\nendmodule\n", platform:'verilog', tool:'verilator', path:'src.v', mainfile:true});
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assert.ok(!(msg.errors && msg.errors.length));
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assert.ok(msg.output);
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assert.ok(msg.warnings.length >= 1);
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assert.ok(msg.warnings.every(w => w.severity == 'warning' && w.line > 0));
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});
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it('should NOT compile CC65 (link error)', function(done) {
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compile('cc65', 'extern void bad();\nint main() {\nbad();\nreturn 0;\n}', 'nes', done, 0, 0, 1, {ignoreErrorPath:true});
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});
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