fixed tests, printFlags, debug info

This commit is contained in:
Steven Hugg 2018-08-29 13:43:46 -04:00
parent 05f5b96256
commit bf584674ab
6 changed files with 36 additions and 20 deletions

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@ -62,7 +62,8 @@ TODO:
- figure out folders for projects for real
- verilog download rom
- why loadState() on verilog kill perf?
- click to break on raster position
- restructure folders
WEB WORKER FORMAT

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@ -1,6 +1,6 @@
import { RAM, RasterVideo, dumpRAM, lookupSymbol } from "./emu";
import { hex } from "./util";
import { hex, printFlags } from "./util";
import { CodeAnalyzer } from "./analysis";
import { disassemble6502 } from "./cpu/disasm6502";
import { disassembleZ80 } from "./cpu/disasmz80";
@ -362,11 +362,7 @@ export function getOpcodeMetadata_6502(opcode, address) {
export function cpuStateToLongString_Z80(c) {
function decodeFlags(flags) {
var flagspec = "SZ-H-VNC";
var s = "";
for (var i=0; i<8; i++)
s += (flags & (128>>i)) ? flagspec.slice(i,i+1) : "-";
return s; // TODO
return printFlags(flags, ["S","Z",,"H",,"V","N","C"], true);
}
return "PC " + hex(c.PC,4) + " " + decodeFlags(c.AF) + "\n"
+ "SP " + hex(c.SP,4) + " IR " + hex(c.IR,4) + "\n"
@ -553,11 +549,7 @@ export function getToolForFilename_z80(fn) {
export function cpuStateToLongString_6809(c) {
function decodeFlags(flags) {
var flagspec = "EFHINZVC";
var s = "";
for (var i=0; i<8; i++)
s += (flags & (128>>i)) ? flagspec.slice(i,i+1) : "-";
return s; // TODO
return printFlags(flags, ["E","F","H","I", "N","Z","V","C"], true);
}
return "PC " + hex(c.PC,4) + " " + decodeFlags(c.CC) + "\n"
+ "SP " + hex(c.SP,4) + "\n"

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@ -11,7 +11,7 @@ const ASTROCADE_PRESETS = [
{id:'03-horcbpal.asm', name:'Paddle Demo'},
];
// TODO: fix keys, more controllers, paddles, vibrato/noise, border color, full refresh
// TODO: fix keys, more controllers, paddles, vibrato/noise, border color, full refresh, debug info
const ASTROCADE_KEYCODE_MAP = makeKeycodeMap([
// player 1
@ -79,6 +79,8 @@ const _BallyAstrocadePlatform = function(mainElement) {
// default palette
for (var i=0; i<8; i++)
palette[i] = ASTROCADE_PALETTE[i];
var refreshlines = 0;
function ramwrite(a:number, v:number) {
ram.mem[a] = v;
@ -90,6 +92,12 @@ const _BallyAstrocadePlatform = function(mainElement) {
}
}
function refreshline(y:number) {
var ofs = y*swidth/4;
for (var i=0; i<swidth/4; i++)
ramwrite(ofs+i, ram.mem[ofs+i]);
}
function magicwrite(a:number, v:number) {
// expand
if (magicop & 0x8) {
@ -142,6 +150,7 @@ const _BallyAstrocadePlatform = function(mainElement) {
function setpalette(a:number, v:number) {
palette[a&7] = ASTROCADE_PALETTE[v&0xff];
refreshlines = sheight;
}
function setbordercolor() {
@ -263,6 +272,10 @@ const _BallyAstrocadePlatform = function(mainElement) {
if (sl == inlin && (inmod & 0x8)) {
cpu.requestInterrupt(infbk);
}
if (refreshlines>0) {
refreshline(sl);
refreshlines--;
}
}
if (!novideo) {
video.updateFrame(0, 0, 0, 0, swidth, verbl+2);

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@ -225,14 +225,12 @@ const _JSNESPlatform = function(mainElement) {
}
getDebugCategories() {
return ['CPU','ZPRAM','Stack','PPU'];
return super.getDebugCategories().concat(['PPU']);
}
getDebugInfo(category, state) {
switch (category) {
case 'CPU': return cpuStateToLongString_6502(state.c);
case 'ZPRAM': return dumpRAM(state.b, 0x0, 0x100);
case 'Stack': return dumpStackToString(this, state.b, 0x100, 0x1ff, 0x100+state.c.SP, 0x20);
case 'PPU': return this.ppuStateToLongString(state.ppu, state.b);
default: return super.getDebugInfo(category, state);
}
}
ppuStateToLongString(ppu, mem) {

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@ -360,3 +360,15 @@ export function safe_extend(deep, dest, src) {
return dest;
}
export function printFlags(val:number, names:string[], r2l:boolean) {
var s = '';
for (var i=0; i<names.length; i++) {
if (names[i]) {
var bit = 1 << (r2l ? names.length-1-i : i);
if (i > 0) s += " ";
s += (val & (1<<bit)) ? names[i] : "-";
}
}
return s;
}

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@ -175,7 +175,7 @@ describe('Worker', function() {
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 2799, 0, 0);
doBuild(msgs, done2, 2781, 0, 0);
});
it('should NOT compile verilog example', function(done) {
var csource = "foobar";
@ -197,7 +197,7 @@ describe('Worker', function() {
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 49357, 0, 0);
doBuild(msgs, done2, 49339, 0, 0);
});
it('should compile verilog assembler file (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm'));
@ -214,7 +214,7 @@ describe('Worker', function() {
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 1997627, 0, 0);
doBuild(msgs, done2, 1997609, 0, 0);
});
it('should NOT preprocess SDCC', function(done) {
compile('sdcc', 'int x=0\n#bah\n', 'mw8080bw', done, 0, 0, 1);