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verilog-vga: updated presets
This commit is contained in:
Steven Hugg
parent
e44a0734dd
commit
cde43b361f
presets/verilog-vga
src/platform
244
presets/verilog-vga/ball_paddle.v
Normal file
244
presets/verilog-vga/ball_paddle.v
Normal file
@ -0,0 +1,244 @@
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`include "hvsync_generator.v"
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`include "digits10.v"
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`include "scoreboard.v"
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/*
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A brick-smashing ball-and-paddle game.
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*/
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module ball_paddle_top(clk, reset, hpaddle, hsync, vsync, rgb);
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input clk;
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input reset;
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input hpaddle;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [9:0] hpos;
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wire [9:0] vpos;
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reg [9:0] paddle_pos; // paddle X position
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reg [9:0] ball_x; // ball X position
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reg [9:0] ball_y; // ball Y position
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reg ball_dir_x; // ball X direction (0=left, 1=right)
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reg ball_speed_x; // ball speed (0=1 pixel/frame, 1=2 pixels/frame)
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reg ball_dir_y; // ball Y direction (0=up, 1=down)
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reg brick_array [0:BRICKS_H*BRICKS_V-1]; // 16*8 = 128 bits
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wire [3:0] score0; // score right digit
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wire [3:0] score1; // score left digit
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wire [3:0] lives; // # lives remaining
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reg incscore; // incscore signal
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reg declives = 0; // TODO
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localparam BRICKS_H = 16; // # of bricks across
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localparam BRICKS_V = 8; // # of bricks down
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localparam BALL_DIR_LEFT = 0;
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localparam BALL_DIR_RIGHT = 1;
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localparam BALL_DIR_DOWN = 1;
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localparam BALL_DIR_UP = 0;
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localparam PADDLE_WIDTH = 63; // horizontal paddle size
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localparam BALL_SIZE = 12; // square ball size
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// video sync generator
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// scoreboard
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wire score_gfx; // output from score generator
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player_stats stats(
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.reset(reset),
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.score0(score0),
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.score1(score1),
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.incscore(incscore),
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.lives(lives),
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.declives(declives)
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);
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scoreboard_generator score_gen(
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.score0(score0),
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.score1(score1),
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.lives(lives),
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.vpos(vpos),
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.hpos(hpos),
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.board_gfx(score_gfx)
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);
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wire [5:0] hcell = hpos[9:4]; // horizontal brick index
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wire [5:0] vcell = vpos[9:4]; // vertical brick index
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wire lr_border = hcell==0 || hcell==31; // along horizontal border?
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// TODO: unsigned compare doesn't work in JS
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wire [9:0] paddle_rel_x = ((hpos-paddle_pos) & 10'h3ff);
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// player paddle graphics signal
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wire paddle_gfx = (vcell == 28) && (paddle_rel_x < PADDLE_WIDTH);
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// difference between ball position and video beam
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wire [9:0] ball_rel_x = (hpos - ball_x);
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wire [9:0] ball_rel_y = (vpos - ball_y);
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// ball graphics signal
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wire ball_gfx = ball_rel_x < BALL_SIZE
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&& ball_rel_y < BALL_SIZE;
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reg main_gfx; // main graphics signal (bricks and borders)
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reg brick_present; // 1 when we are drawing a brick
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reg [6:0] brick_index;// index into array of current brick
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// brick graphics signal
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wire brick_gfx = lr_border || (brick_present && vpos[3:1] != 0 && hpos[4:2] != 4);
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// scan bricks: compute brick_index and brick_present flag
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always @(posedge clk)
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// see if we are scanning brick area
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if (vpos[9:7] == 1 && !lr_border)
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begin
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// every 16th pixel, starting at 8
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if (hpos[4:0] == 8) begin
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// compute brick index
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brick_index <= {vpos[6:4], hpos[8:5]};
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end
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// every 17th pixel
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else if (hpos[4:0] == 9) begin
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// load brick bit from array
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brick_present <= !brick_array[brick_index];
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end
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end else begin
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brick_present <= 0;
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end
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// only works when paddle at bottom of screen!
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// (we don't want to mess w/ paddle position during visible portion)
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always @(posedge hsync)
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if (!hpaddle)
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paddle_pos <= vpos;
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// 1 when ball signal intersects main (brick + border) signal
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wire ball_pixel_collide = main_gfx & ball_gfx;
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reg ball_collide_paddle = 0;
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reg [3:0] ball_collide_bits = 0;
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// compute ball collisions with paddle and playfield
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always @(posedge clk)
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// clear all collide bits for frame
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if (vsync) begin
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ball_collide_bits <= 0;
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ball_collide_paddle <= 0;
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end else begin
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if (ball_pixel_collide) begin
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// did we collide w/ paddle?
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if (paddle_gfx) begin
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ball_collide_paddle <= 1;
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end
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// ball has 4 collision quadrants
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if (!ball_rel_x[2] & !ball_rel_y[2]) ball_collide_bits[0] <= 1;
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if (ball_rel_x[2] & !ball_rel_y[2]) ball_collide_bits[1] <= 1;
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if (!ball_rel_x[2] & ball_rel_y[2]) ball_collide_bits[2] <= 1;
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if (ball_rel_x[2] & ball_rel_y[2]) ball_collide_bits[3] <= 1;
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end
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end
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// compute ball collisions with brick and increment score
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always @(posedge clk)
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if (ball_pixel_collide && brick_present) begin
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brick_array[brick_index] <= 1;
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incscore <= 1; // increment score
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end else begin
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incscore <= 0; // reset incscore
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end
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// computes position of ball in relation to center of paddle
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wire signed [9:0] ball_paddle_dx = ball_x - paddle_pos + 8;
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// ball bounce: determine new velocity/direction
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always @(posedge vsync or posedge reset)
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begin
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if (reset) begin
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ball_dir_y <= BALL_DIR_DOWN;
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end else
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// ball collided with paddle?
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if (ball_collide_paddle) begin
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// bounces upward off of paddle
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ball_dir_y <= BALL_DIR_UP;
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// which side of paddle, left/right?
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ball_dir_x <= (ball_paddle_dx < 20) ? BALL_DIR_LEFT : BALL_DIR_RIGHT;
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// hitting with edge of paddle makes it fast
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ball_speed_x <= ball_collide_bits[3:0] != 4'b1100;
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end else begin
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// collided with playfield
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// TODO: can still slip through corners
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// compute left/right bounce
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casez (ball_collide_bits[3:0])
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4'b01?1: ball_dir_x <= BALL_DIR_RIGHT; // left edge/corner
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4'b1101: ball_dir_x <= BALL_DIR_RIGHT; // left corner
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4'b101?: ball_dir_x <= BALL_DIR_LEFT; // right edge/corner
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4'b1110: ball_dir_x <= BALL_DIR_LEFT; // right corner
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default: ;
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endcase
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// compute top/bottom bounce
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casez (ball_collide_bits[3:0])
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4'b1011: ball_dir_y <= BALL_DIR_DOWN;
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4'b0111: ball_dir_y <= BALL_DIR_DOWN;
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4'b001?: ball_dir_y <= BALL_DIR_DOWN;
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4'b0001: ball_dir_y <= BALL_DIR_DOWN;
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4'b0100: ball_dir_y <= BALL_DIR_UP;
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4'b1?00: ball_dir_y <= BALL_DIR_UP;
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4'b1101: ball_dir_y <= BALL_DIR_UP;
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4'b1110: ball_dir_y <= BALL_DIR_UP;
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default: ;
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endcase
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end
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end
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// ball motion: update ball position
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always @(negedge vsync or posedge reset)
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begin
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if (reset) begin
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// reset ball position to top center
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ball_x <= 256;
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ball_y <= 320;
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end else begin
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// move ball horizontal and vertical position
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if (ball_dir_x == BALL_DIR_RIGHT)
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ball_x <= ball_x + (ball_speed_x?1:0) + 1;
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else
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ball_x <= ball_x - (ball_speed_x?1:0) - 1;
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ball_y <= ball_y + (ball_dir_y==BALL_DIR_DOWN?1:-1);
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end
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end
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// compute main_gfx
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always @(*)
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begin
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case (vpos[9:4])
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0,1,2: main_gfx = score_gfx; // scoreboard
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3: main_gfx = 0;
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4: main_gfx = 1; // top border
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8,9,10,11,12,13,14,15: main_gfx = brick_gfx; // brick rows 1-8
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28: main_gfx = paddle_gfx | lr_border; // paddle
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29: main_gfx = hpos[0] ^ vpos[0]; // bottom border
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default: main_gfx = lr_border; // left/right borders
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endcase
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end
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// combine signals to RGB output
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wire grid_gfx = (((hpos&15)==0) || ((vpos&15)==0));
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wire r = display_on && (ball_gfx | paddle_gfx);
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wire g = display_on && (main_gfx | ball_gfx);
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wire b = display_on && (grid_gfx | ball_gfx | brick_present);
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assign rgb = {b,g,r};
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endmodule
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84
presets/verilog-vga/chardisplay.v
Normal file
84
presets/verilog-vga/chardisplay.v
Normal file
@ -0,0 +1,84 @@
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`include "hvsync_generator.v"
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`include "digits10.v"
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`include "ram.v"
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/*
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Displays a grid of digits on the CRT using a RAM module.
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*/
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module test_ram1_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [9:0] hpos;
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wire [9:0] vpos;
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wire [9:0] ram_addr;
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wire [7:0] ram_read;
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reg [7:0] ram_write;
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reg ram_writeenable = 0;
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// RAM to hold 32x32 array of bytes
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RAM_sync ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(ram_addr),
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.we(ram_writeenable)
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);
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [4:0] row = vpos[7:3]; // 5-bit row, vpos / 8
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wire [4:0] col = hpos[7:3]; // 5-bit column, hpos / 8
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wire [2:0] rom_yofs = vpos[2:0]; // scanline of cell
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wire [4:0] rom_bits; // 5 pixels per scanline
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wire [3:0] digit = ram_read[3:0]; // read digit from RAM
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wire [2:0] xofs = hpos[2:0]; // which pixel to draw (0-7)
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assign ram_addr = {row,col}; // 10-bit RAM address
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// digits ROM
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digits10_case numbers(
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.digit(digit),
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.yofs(rom_yofs),
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.bits(rom_bits)
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);
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// extract bit from ROM output
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wire r = display_on && 0;
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wire g = display_on && rom_bits[~xofs];
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wire b = display_on && 0;
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assign rgb = {b,g,r};
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// increment the current RAM cell
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always @(posedge clk)
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case (hpos[2:0])
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// on 7th pixel of cell
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6: begin
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// increment RAM cell
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ram_write <= (ram_read + 1);
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// only enable write on last scanline of cell
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ram_writeenable <= (vpos[2:0] == 7);
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end
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// on 8th pixel of cell
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7: begin
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// disable write
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ram_writeenable <= 0;
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end
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endcase
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endmodule
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211
presets/verilog-vga/digits10.v
Normal file
211
presets/verilog-vga/digits10.v
Normal file
@ -0,0 +1,211 @@
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`ifndef DIGITS10_H
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`define DIGITS10_H
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`include "hvsync_generator.v"
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/*
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ROM module with 5x5 bitmaps for the digits 0-9.
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digits10_case - Uses the case statement.
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digits10_array - Uses an array and initial block.
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These two modules are functionally equivalent.
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*/
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// module for 10-digit bitmap ROM
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module digits10_case(digit, yofs, bits);
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input [3:0] digit; // digit 0-9
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input [2:0] yofs; // vertical offset (0-4)
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output reg [4:0] bits; // output (5 bits)
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// combine {digit,yofs} into single ROM address
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wire [6:0] caseexpr = {digit,yofs};
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always @(*)
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case (caseexpr)/*{w:5,h:5,count:10}*/
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7'o00: bits = 5'b11111;
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7'o01: bits = 5'b10001;
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7'o02: bits = 5'b10001;
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7'o03: bits = 5'b10001;
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7'o04: bits = 5'b11111;
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7'o10: bits = 5'b01100;
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7'o11: bits = 5'b00100;
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7'o12: bits = 5'b00100;
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7'o13: bits = 5'b00100;
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7'o14: bits = 5'b11111;
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7'o20: bits = 5'b11111;
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7'o21: bits = 5'b00001;
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7'o22: bits = 5'b11111;
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7'o23: bits = 5'b10000;
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7'o24: bits = 5'b11111;
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7'o30: bits = 5'b11111;
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7'o31: bits = 5'b00001;
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7'o32: bits = 5'b11111;
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7'o33: bits = 5'b00001;
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7'o34: bits = 5'b11111;
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7'o40: bits = 5'b10001;
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7'o41: bits = 5'b10001;
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7'o42: bits = 5'b11111;
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7'o43: bits = 5'b00001;
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7'o44: bits = 5'b00001;
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7'o50: bits = 5'b11111;
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7'o51: bits = 5'b10000;
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7'o52: bits = 5'b11111;
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7'o53: bits = 5'b00001;
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7'o54: bits = 5'b11111;
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7'o60: bits = 5'b11111;
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7'o61: bits = 5'b10000;
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7'o62: bits = 5'b11111;
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7'o63: bits = 5'b10001;
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7'o64: bits = 5'b11111;
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7'o70: bits = 5'b11111;
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7'o71: bits = 5'b00001;
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7'o72: bits = 5'b00001;
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7'o73: bits = 5'b00001;
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7'o74: bits = 5'b00001;
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7'o100: bits = 5'b11111;
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7'o101: bits = 5'b10001;
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7'o102: bits = 5'b11111;
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7'o103: bits = 5'b10001;
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7'o104: bits = 5'b11111;
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7'o110: bits = 5'b11111;
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7'o111: bits = 5'b10001;
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7'o112: bits = 5'b11111;
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7'o113: bits = 5'b00001;
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7'o114: bits = 5'b11111;
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default: bits = 0;
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endcase
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endmodule
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module digits10_array(digit, yofs, bits);
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input [3:0] digit; // digit 0-9
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input [2:0] yofs; // vertical offset (0-4)
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output [4:0] bits; // output (5 bits)
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reg [4:0] bitarray[0:15][0:4]; // ROM array (16 x 5 x 5 bits)
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assign bits = bitarray[digit][yofs]; // assign module output
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integer i,j;
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initial begin/*{w:5,h:5,count:10}*/
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bitarray[0][0] = 5'b11111;
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bitarray[0][1] = 5'b10001;
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bitarray[0][2] = 5'b10001;
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bitarray[0][3] = 5'b10001;
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bitarray[0][4] = 5'b11111;
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bitarray[1][0] = 5'b01100;
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bitarray[1][1] = 5'b00100;
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bitarray[1][2] = 5'b00100;
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bitarray[1][3] = 5'b00100;
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bitarray[1][4] = 5'b11111;
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bitarray[2][0] = 5'b11111;
|
||||
bitarray[2][1] = 5'b00001;
|
||||
bitarray[2][2] = 5'b11111;
|
||||
bitarray[2][3] = 5'b10000;
|
||||
bitarray[2][4] = 5'b11111;
|
||||
|
||||
bitarray[3][0] = 5'b11111;
|
||||
bitarray[3][1] = 5'b00001;
|
||||
bitarray[3][2] = 5'b11111;
|
||||
bitarray[3][3] = 5'b00001;
|
||||
bitarray[3][4] = 5'b11111;
|
||||
|
||||
bitarray[4][0] = 5'b10001;
|
||||
bitarray[4][1] = 5'b10001;
|
||||
bitarray[4][2] = 5'b11111;
|
||||
bitarray[4][3] = 5'b00001;
|
||||
bitarray[4][4] = 5'b00001;
|
||||
|
||||
bitarray[5][0] = 5'b11111;
|
||||
bitarray[5][1] = 5'b10000;
|
||||
bitarray[5][2] = 5'b11111;
|
||||
bitarray[5][3] = 5'b00001;
|
||||
bitarray[5][4] = 5'b11111;
|
||||
|
||||
bitarray[6][0] = 5'b11111;
|
||||
bitarray[6][1] = 5'b10000;
|
||||
bitarray[6][2] = 5'b11111;
|
||||
bitarray[6][3] = 5'b10001;
|
||||
bitarray[6][4] = 5'b11111;
|
||||
|
||||
bitarray[7][0] = 5'b11111;
|
||||
bitarray[7][1] = 5'b00001;
|
||||
bitarray[7][2] = 5'b00001;
|
||||
bitarray[7][3] = 5'b00001;
|
||||
bitarray[7][4] = 5'b00001;
|
||||
|
||||
bitarray[8][0] = 5'b11111;
|
||||
bitarray[8][1] = 5'b10001;
|
||||
bitarray[8][2] = 5'b11111;
|
||||
bitarray[8][3] = 5'b10001;
|
||||
bitarray[8][4] = 5'b11111;
|
||||
|
||||
bitarray[9][0] = 5'b11111;
|
||||
bitarray[9][1] = 5'b10001;
|
||||
bitarray[9][2] = 5'b11111;
|
||||
bitarray[9][3] = 5'b00001;
|
||||
bitarray[9][4] = 5'b11111;
|
||||
|
||||
// clear unused array entries
|
||||
for (i = 10; i <= 15; i++)
|
||||
for (j = 0; j <= 4; j++)
|
||||
bitarray[i][j] = 0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// test module
|
||||
module test_numbers_top(clk, reset, hsync, vsync, rgb);
|
||||
|
||||
input clk, reset;
|
||||
output hsync, vsync;
|
||||
output [2:0] rgb;
|
||||
|
||||
wire display_on;
|
||||
wire [8:0] hpos;
|
||||
wire [8:0] vpos;
|
||||
|
||||
hvsync_generator hvsync_gen(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.hsync(hsync),
|
||||
.vsync(vsync),
|
||||
.display_on(display_on),
|
||||
.hpos(hpos),
|
||||
.vpos(vpos)
|
||||
);
|
||||
|
||||
wire [3:0] digit = hpos[7:4];
|
||||
wire [2:0] xofs = hpos[3:1];
|
||||
wire [2:0] yofs = vpos[3:1];
|
||||
wire [4:0] bits;
|
||||
|
||||
digits10_array numbers(
|
||||
.digit(digit),
|
||||
.yofs(yofs),
|
||||
.bits(bits)
|
||||
);
|
||||
|
||||
wire r = display_on && 0;
|
||||
wire g = display_on && bits[xofs ^ 3'b111];
|
||||
wire b = display_on && 0;
|
||||
assign rgb = {b,g,r};
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
@ -3,7 +3,8 @@
|
||||
`define HVSYNC_GENERATOR_H
|
||||
|
||||
/*
|
||||
Video sync generator, used to drive a simulated CRT.
|
||||
Video sync generator, used to drive a VGA monitor.
|
||||
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
|
||||
To use:
|
||||
- Wire the hsync and vsync signals to top level outputs
|
||||
- Add a 3-bit (or more) "rgb" output to the top level
|
||||
@ -15,20 +16,20 @@ module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
|
||||
input reset;
|
||||
output reg hsync, vsync;
|
||||
output display_on;
|
||||
output reg [8:0] hpos;
|
||||
output reg [8:0] vpos;
|
||||
output reg [9:0] hpos;
|
||||
output reg [9:0] vpos;
|
||||
|
||||
// declarations for TV-simulator sync parameters
|
||||
// horizontal constants
|
||||
parameter H_DISPLAY = 256; // horizontal display width
|
||||
parameter H_BACK = 23; // horizontal left border (back porch)
|
||||
parameter H_FRONT = 7; // horizontal right border (front porch)
|
||||
parameter H_SYNC = 23; // horizontal sync width
|
||||
parameter H_DISPLAY = 640; // horizontal display width
|
||||
parameter H_BACK = 48; // horizontal left border (back porch)
|
||||
parameter H_FRONT = 16; // horizontal right border (front porch)
|
||||
parameter H_SYNC = 96; // horizontal sync width
|
||||
// vertical constants
|
||||
parameter V_DISPLAY = 240; // vertical display height
|
||||
parameter V_TOP = 5; // vertical top border
|
||||
parameter V_BOTTOM = 14; // vertical bottom border
|
||||
parameter V_SYNC = 3; // vertical sync # lines
|
||||
parameter V_DISPLAY = 480; // vertical display height
|
||||
parameter V_TOP = 33; // vertical top border
|
||||
parameter V_BOTTOM = 10; // vertical bottom border
|
||||
parameter V_SYNC = 2; // vertical sync # lines
|
||||
// derived constants
|
||||
parameter H_SYNC_START = H_DISPLAY + H_FRONT;
|
||||
parameter H_SYNC_END = H_DISPLAY + H_FRONT + H_SYNC - 1;
|
||||
|
||||
114
presets/verilog-vga/scoreboard.v
Normal file
114
presets/verilog-vga/scoreboard.v
Normal file
@ -0,0 +1,114 @@
|
||||
|
||||
`ifndef SCOREBOARD_H
|
||||
`define SCOREBOARD_H
|
||||
|
||||
`include "hvsync_generator.v"
|
||||
`include "digits10.v"
|
||||
|
||||
/*
|
||||
player_stats - Holds two-digit score and one-digit lives counter.
|
||||
scoreboard_generator - Outputs video signal with score/lives digits.
|
||||
*/
|
||||
|
||||
module player_stats(reset, score0, score1, lives, incscore, declives);
|
||||
|
||||
input reset;
|
||||
output reg [3:0] score0;
|
||||
output reg [3:0] score1;
|
||||
input incscore;
|
||||
output reg [3:0] lives;
|
||||
input declives;
|
||||
|
||||
always @(posedge incscore or posedge reset)
|
||||
begin
|
||||
if (reset) begin
|
||||
score0 <= 0;
|
||||
score1 <= 0;
|
||||
end else if (score0 == 9) begin
|
||||
score0 <= 0;
|
||||
score1 <= score1 + 1;
|
||||
end else begin
|
||||
score0 <= score0 + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge declives or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
lives <= 3;
|
||||
else if (lives != 0)
|
||||
lives <= lives - 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module scoreboard_generator(score0, score1, lives, vpos, hpos, board_gfx);
|
||||
|
||||
input [3:0] score0;
|
||||
input [3:0] score1;
|
||||
input [3:0] lives;
|
||||
input [9:0] vpos;
|
||||
input [9:0] hpos;
|
||||
output board_gfx;
|
||||
|
||||
reg [3:0] score_digit;
|
||||
reg [4:0] score_bits;
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
case (hpos[8:6])
|
||||
1: score_digit = score1;
|
||||
2: score_digit = score0;
|
||||
6: score_digit = lives;
|
||||
default: score_digit = 15; // no digit
|
||||
endcase
|
||||
end
|
||||
|
||||
digits10_array digits(
|
||||
.digit(score_digit),
|
||||
.yofs(vpos[5:3]),
|
||||
.bits(score_bits)
|
||||
);
|
||||
|
||||
assign board_gfx = score_bits[hpos[5:3] ^ 3'b111];
|
||||
|
||||
endmodule
|
||||
|
||||
module scoreboard_top(clk, reset, hsync, vsync, rgb);
|
||||
|
||||
input clk, reset;
|
||||
output hsync, vsync;
|
||||
output [2:0] rgb;
|
||||
wire display_on;
|
||||
wire [9:0] hpos;
|
||||
wire [9:0] vpos;
|
||||
|
||||
wire board_gfx;
|
||||
|
||||
hvsync_generator hvsync_gen(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.hsync(hsync),
|
||||
.vsync(vsync),
|
||||
.display_on(display_on),
|
||||
.hpos(hpos),
|
||||
.vpos(vpos)
|
||||
);
|
||||
|
||||
scoreboard_generator scoreboard_gen(
|
||||
.score0(0),
|
||||
.score1(1),
|
||||
.lives(3),
|
||||
.vpos(vpos),
|
||||
.hpos(hpos),
|
||||
.board_gfx(board_gfx)
|
||||
);
|
||||
|
||||
wire r = display_on && board_gfx;
|
||||
wire g = display_on && board_gfx;
|
||||
wire b = display_on && board_gfx;
|
||||
assign rgb = {b,g,r};
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
42
presets/verilog-vga/starfield.v
Normal file
42
presets/verilog-vga/starfield.v
Normal file
@ -0,0 +1,42 @@
|
||||
|
||||
`include "hvsync_generator.v"
|
||||
`include "lfsr.v"
|
||||
|
||||
/*
|
||||
Scrolling starfield generator using a period (2^16-1) LFSR.
|
||||
*/
|
||||
|
||||
module starfield_top(clk, reset, hsync, vsync, rgb);
|
||||
|
||||
input clk, reset;
|
||||
output hsync, vsync;
|
||||
output [2:0] rgb;
|
||||
wire display_on;
|
||||
wire [9:0] hpos;
|
||||
wire [9:0] vpos;
|
||||
wire [15:0] lfsr;
|
||||
|
||||
hvsync_generator hvsync_gen(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.hsync(hsync),
|
||||
.vsync(vsync),
|
||||
.display_on(display_on),
|
||||
.hpos(hpos),
|
||||
.vpos(vpos)
|
||||
);
|
||||
|
||||
// enable LFSR only in 512x512 area
|
||||
wire star_enable = !hpos[9] & !vpos[9];
|
||||
|
||||
// LFSR with period = 2^16-1 = 256*256-1
|
||||
LFSR #(16'b1000000001011,0) lfsr_gen(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(star_enable),
|
||||
.lfsr(lfsr));
|
||||
|
||||
wire star_on = &lfsr[15:9]; // all 7 bits must be set
|
||||
assign rgb = display_on && star_on ? lfsr[2:0] : 0;
|
||||
|
||||
endmodule
|
||||
@ -11,8 +11,8 @@ module test_hvsync_top(clk, reset, hsync, vsync, rgb);
|
||||
output hsync, vsync;
|
||||
output [2:0] rgb;
|
||||
wire display_on;
|
||||
wire [8:0] hpos;
|
||||
wire [8:0] vpos;
|
||||
wire [9:0] hpos;
|
||||
wire [9:0] vpos;
|
||||
|
||||
hvsync_generator hvsync_gen(
|
||||
.clk(clk),
|
||||
|
||||
@ -761,6 +761,9 @@ var VerilogPlatform = function(mainElement, options) {
|
||||
var VERILOG_VGA_PRESETS = [
|
||||
{id:'hvsync_generator.v', name:'Video Sync Generator'},
|
||||
{id:'test_hvsync.v', name:'Test Pattern'},
|
||||
{id:'chardisplay.v', name:'RAM Text Display'},
|
||||
{id:'starfield.v', name:'Scrolling Starfield'},
|
||||
{id:'ball_paddle.v', name:'Brick Smash Game'},
|
||||
];
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user