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mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-06-13 09:29:35 +00:00

fixed verilog inline asm

This commit is contained in:
Steven Hugg 2018-07-11 23:59:35 -05:00
parent f466afa085
commit d35a328246
5 changed files with 49 additions and 22 deletions

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@ -46,6 +46,7 @@ TODO:
- show tool-specific (readonly) include files - show tool-specific (readonly) include files
- verilog debugging makes it slow - verilog debugging makes it slow
- fix VCS mame - fix VCS mame
- checkmarks for active window
WEB WORKER FORMAT WEB WORKER FORMAT

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@ -9,17 +9,19 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
wire display_on; wire display_on;
wire [8:0] hpos; wire [8:0] hpos;
wire [8:0] vpos; wire [8:0] vpos;
reg ball_reset;
// 9-bit ball timers
reg [8:0] ball_htimer; reg [8:0] ball_htimer;
reg [8:0] ball_vtimer; reg [8:0] ball_vtimer;
// motion codes // 4-bit motion codes
reg [3:0] ball_horiz_move; reg [3:0] ball_horiz_move;
reg [3:0] ball_vert_move; reg [3:0] ball_vert_move;
// stop codes // 4-bit stop codes
localparam ball_horiz_stop = 4'd12; localparam ball_horiz_stop = 4'd11;
localparam ball_vert_stop = 4'd11; localparam ball_vert_stop = 4'd10;
// 5-bit constants to load into counters // 5-bit constants to load into counters
localparam ball_horiz_prefix = 5'b01100; // 192 localparam ball_horiz_prefix = 5'b01100; // 192
@ -36,11 +38,10 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
); );
// update horizontal timer // update horizontal timer
always @(posedge clk or posedge reset) begin always @(posedge clk or posedge ball_reset)
if (reset || ball_htimer == 0) begin begin
if (reset) // center-ish of screen if (ball_reset || &ball_htimer) begin
ball_htimer <= {5'b11000, ball_horiz_move}; if (ball_reset || &ball_vtimer) // nudge ball in horiz. dir
else if (ball_vtimer == 0) // nudge ball in horiz. dir
ball_htimer <= {ball_horiz_prefix, ball_horiz_move}; ball_htimer <= {ball_horiz_prefix, ball_horiz_move};
else // reset timer but don't move ball horizontally else // reset timer but don't move ball horizontally
ball_htimer <= {ball_horiz_prefix, ball_horiz_stop}; ball_htimer <= {ball_horiz_prefix, ball_horiz_stop};
@ -49,15 +50,22 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
end end
// update vertical timer // update vertical timer
always @(posedge hsync or posedge reset) always @(posedge hsync or posedge ball_reset)
begin begin
if (reset) // center-ish of screen if (ball_reset || &ball_vtimer) // reset timer
ball_vtimer <= {5'b11000, ball_vert_move};
else if (ball_vtimer == 0) // reset timer
ball_vtimer <= {ball_vert_prefix, ball_vert_move}; ball_vtimer <= {ball_vert_prefix, ball_vert_move};
else else
ball_vtimer <= ball_vtimer + 1; ball_vtimer <= ball_vtimer + 1;
end end
// reset ball position
always @(posedge clk or posedge reset)
begin
if (reset)
ball_reset <= 1;
else if (hpos == 128 && vpos == 128)
ball_reset <= 0;
end
// collide with vertical and horizontal boundaries // collide with vertical and horizontal boundaries
wire ball_vert_collide = ball_vgfx && vpos >= 240; wire ball_vert_collide = ball_vgfx && vpos >= 240;
@ -67,18 +75,18 @@ module ball_slip_counter_top(clk, reset, hsync, vsync, rgb);
always @(posedge ball_vert_collide or posedge reset) always @(posedge ball_vert_collide or posedge reset)
begin begin
if (reset) if (reset)
ball_vert_move <= 4'd10; ball_vert_move <= 4'd9;
else else
ball_vert_move <= 4'b0110 ^ ball_vert_move; // change dir. ball_vert_move <= (4'd9 ^ 4'd11) ^ ball_vert_move; // change dir.
end end
// horizontal bounce // horizontal bounce
always @(posedge ball_horiz_collide or posedge reset) always @(posedge ball_horiz_collide or posedge reset)
begin begin
if (reset) if (reset)
ball_horiz_move <= 4'd11; ball_horiz_move <= 4'd10;
else else
ball_horiz_move <= 4'b0110 ^ ball_horiz_move; // change dir. ball_horiz_move <= (4'd10 ^ 4'd12) ^ ball_horiz_move; // change dir.
end end
// compute ball display // compute ball display

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@ -119,7 +119,7 @@ function getToolForFilename_6502(fn:string) : string {
return "dasm"; // .a return "dasm"; // .a
} }
abstract class Base6502Platform extends BaseDebugPlatform { export abstract class Base6502Platform extends BaseDebugPlatform {
newCPU(membus : MemoryBus) { newCPU(membus : MemoryBus) {
var cpu = new jt.M6502(); var cpu = new jt.M6502();
@ -284,7 +284,7 @@ function BusProbe(bus : MemoryBus) {
} }
} }
abstract class BaseZ80Platform extends BaseDebugPlatform { export abstract class BaseZ80Platform extends BaseDebugPlatform {
_cpu; _cpu;
probe; probe;
@ -421,7 +421,7 @@ function getToolForFilename_z80(fn) {
declare var FS, ENV, Module; // mame emscripten declare var FS, ENV, Module; // mame emscripten
// TODO: make class // TODO: make class
var BaseMAMEPlatform = function() { export function BaseMAMEPlatform() {
var self = this; var self = this;

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@ -1158,17 +1158,18 @@ function compileInlineASM(code, platform, options, errors, asmlines) {
function compileVerilator(step) { function compileVerilator(step) {
loadNative("verilator_bin"); loadNative("verilator_bin");
loadGen("worker/verilator2js"); loadGen("worker/verilator2js");
var code = step.code;
var platform = step.platform || 'verilog'; var platform = step.platform || 'verilog';
var errors = []; var errors = [];
var asmlines = []; var asmlines = [];
code = compileInlineASM(code, platform, step, errors, asmlines); step.code = compileInlineASM(step.code, platform, step, errors, asmlines);
var code = step.code;
var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?:)?(\d+)?[:]?\s*(.+)/i, 3, 4); var match_fn = makeErrorMatcher(errors, /%(.+?): (.+?:)?(\d+)?[:]?\s*(.+)/i, 3, 4);
var verilator_mod = verilator_bin({ var verilator_mod = verilator_bin({
instantiateWasm: moduleInstFn('verilator_bin'), instantiateWasm: moduleInstFn('verilator_bin'),
noInitialRun:true, noInitialRun:true,
print:print_fn, print:print_fn,
printErr:match_fn, printErr:match_fn,
//TOTAL_MEMORY:64*1024*1024,
}); });
var topmod = detectTopModuleName(code); var topmod = detectTopModuleName(code);
var FS = verilator_mod['FS']; var FS = verilator_mod['FS'];

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@ -165,6 +165,23 @@ describe('Worker', function() {
doBuild(msgs, done2, 2782, 0, 0); doBuild(msgs, done2, 2782, 0, 0);
}); });
it('should compile verilog inline assembler (JSASM)', function(done) { it('should compile verilog inline assembler (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/racing_game_cpu.v'));
var dependfiles = ["hvsync_generator.v", "sprite_bitmap.v", "sprite_renderer.v", "cpu8.v"];
var depends = [];
for (var dfile of dependfiles) {
var code = ab2str(fs.readFileSync('presets/verilog/' + dfile));
depends.push({filename:dfile, data:code, prefix:"verilog"});
}
var msgs = [{code:csource, platform:"verilog", tool:"verilator", dependencies:depends, path:'racing_game_cpu.v'}];
var done2 = function(err, msg) {
var jscode = msg.output.code;
var fn = new Function(jscode);
assert.ok(fn);
done(err, msg);
};
doBuild(msgs, done2, 49317, 0, 0);
});
it('should compile verilog assembler file (JSASM)', function(done) {
var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm')); var csource = ab2str(fs.readFileSync('presets/verilog/test2.asm'));
var dependfiles = ["hvsync_generator.v", "font_cp437_8x8.v", "ram.v", "tile_renderer.v", "sprite_scanline_renderer.v", "lfsr.v", "sound_generator.v", "cpu16.v", "cpu_platform.v"]; var dependfiles = ["hvsync_generator.v", "font_cp437_8x8.v", "ram.v", "tile_renderer.v", "sprite_scanline_renderer.v", "lfsr.v", "sound_generator.v", "cpu16.v", "cpu_platform.v"];
var depends = []; var depends = [];