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verilog: added signed property to data types

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This commit is contained in:
Steven Hugg 2021-07-15 11:41:41 -05:00
parent 8d756ff363
commit ff4bbaccdb
5 changed files with 27 additions and 19 deletions
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1
src/common/hdl/hdltypes.ts
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@ -26,6 +26,7 @@ export interface HDLModuleTrace extends HDLModuleRunner {
export interface HDLLogicType extends HDLSourceObject {
left: number;
right: number;
signed: boolean;
}
export interface HDLUnpackArray extends HDLSourceObject {

22
src/common/hdl/hdlwasm.ts
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@ -1001,19 +1001,25 @@ export class HDLModuleWASM implements HDLModuleRunner {
if (isLogicType(tsrc) && isLogicType(tdst) && tsrc.right == 0 && tdst.right == 0) {
if (tsrc.left == tdst.left) {
return val;
} else if (tsrc.left <= 31 && tdst.left <= 31) {
return val;
} else if (tsrc.left > 31 && tdst.left > 31) {
return val;
} else if (tsrc.left > 63 || tdst.left > 63) {
throw new HDLError(tdst, `values > 64 bits not supported`);
}
// TODO: signed?
else if (tsrc.left <= 31 && tdst.left > 31) { // 32 -> 64
return this.bmod.i64.extend_u(val);
} else if (tsrc.left <= 31 && tdst.left <= 31 && !tsrc.signed && !tdst.signed) {
return val;
} else if (tsrc.left > 31 && tdst.left > 31 && !tsrc.signed && !tdst.signed) {
return val;
} else if (tsrc.left == 7 && tdst.left == 31 && tsrc.signed && tdst.signed) {
return this.bmod.i32.extend8_s(val);
} else if (tsrc.left == 15 && tdst.left == 31 && tsrc.signed && tdst.signed) {
return this.bmod.i32.extend16_s(val);
} else if (tsrc.left <= 31 && tdst.left > 31) { // 32 -> 64
if (tsrc.signed)
return this.bmod.i64.extend_s(val);
else
return this.bmod.i64.extend_u(val);
} else if (tsrc.left > 31 && tdst.left <= 31) { // 64 -> 32
return this.bmod.i32.wrap(val);
}
throw new HDLError([tsrc, tdst], `cannot cast ${tsrc.left}/${tsrc.signed} to ${tdst.left}/${tdst.signed}`);
}
throw new HDLError([tsrc, tdst], `cannot cast`);
}

21
src/common/hdl/vxmlparser.ts
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@ -115,16 +115,16 @@ export class VerilogXMLParser implements HDLUnit {
constructor() {
// TODO: other types?
this.dtypes['QData'] = {left:63, right:0};
this.dtypes['IData'] = {left:31, right:0};
this.dtypes['SData'] = {left:15, right:0};
this.dtypes['CData'] = {left:7, right:0};
this.dtypes['byte'] = {left:7, right:0};
this.dtypes['shortint'] = {left:15, right:0};
this.dtypes['int'] = {left:31, right:0};
this.dtypes['integer'] = {left:31, right:0};
this.dtypes['longint'] = {left:63, right:0};
this.dtypes['time'] = {left:63, right:0};
this.dtypes['QData'] = {left:63, right:0, signed:false};
this.dtypes['IData'] = {left:31, right:0, signed:false};
this.dtypes['SData'] = {left:15, right:0, signed:false};
this.dtypes['CData'] = {left:7, right:0, signed:false};
this.dtypes['byte'] = {left:7, right:0, signed:true};
this.dtypes['shortint'] = {left:15, right:0, signed:true};
this.dtypes['int'] = {left:31, right:0, signed:true};
this.dtypes['integer'] = {left:31, right:0, signed:true};
this.dtypes['longint'] = {left:63, right:0, signed:true};
this.dtypes['time'] = {left:63, right:0, signed:false};
}
defer(fn: () => void) {
@ -475,6 +475,7 @@ export class VerilogXMLParser implements HDLUnit {
$loc: this.parseSourceLocation(node),
left: parseInt(node.attrs['left'] || "0"),
right: parseInt(node.attrs['right'] || "0"),
signed: node.attrs['signed'] == 'true'
}
dtype = dlogic;
break;

BIN
src/worker/wasm/verilator_bin.wasm
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2
src/worker/workermain.ts
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@ -1816,7 +1816,7 @@ function compileVerilator(step:BuildStep) {
starttime();
var xmlPath = `obj_dir/V${topmod}.xml`;
try {
var args = ["--cc", "-O3"/*abcdefstzsuka*/,
var args = ["--cc", "-O3",
"-DEXT_INLINE_ASM", "-DTOPMOD__"+topmod, "-D__8BITWORKSHOP__",
"-Wall",
"-Wno-DECLFILENAME", "-Wno-UNUSED", "-Wno-EOFNEWLINE", "-Wno-PROCASSWIRE",