14 Commits

Author	SHA1	Message	Date
Steven Hugg	706a24c96a	updated presets, changed array syntax, ice40 fpga examples	2018-10-08 20:38:39 -04:00
Steven Hugg	716205a2b1	fixed unit tests	2018-10-03 15:06:48 -04:00
Steven Hugg	5c5ee32a66	verilog pixel editor fix (array index must be unsized)	2018-10-02 11:24:29 -04:00
Steven Hugg	1a7480ea65	Merge branch 'master' of github.com:sehugg/8bitworkshop	2018-10-01 13:36:56 -04:00
Steven Hugg	7e00cc898b	verilog preset comments	2018-10-01 13:36:26 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	2dbc60aa2e	updated presets; verilog code dup detect; need to handle local/ include files somehow	2018-07-31 23:03:53 -04:00
Steven Hugg	e0e3e0bf61	paddles.v	2018-06-03 19:46:33 -07:00
Steven Hugg	0ee201b9e8	update presets; redir.html expire	2018-06-01 10:33:37 -07:00
Steven Hugg	db005dc98e	can scroll scope when paused; updates to presets	2018-02-28 12:13:59 -06:00
Steven Hugg	8f1563f88e	sync vs async RAM	2018-02-28 09:26:37 -06:00
Steven Hugg	b5c74234f3	smoother scope transition; slowest/fastest buttons; video width tweak	2018-02-27 14:09:27 -06:00
Steven Hugg	6fa030f398	optimized scanline renderer	2018-02-25 10:53:52 -06:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00