10 Commits

Author	SHA1	Message	Date
Steven Hugg	706a24c96a	updated presets, changed array syntax, ice40 fpga examples	2018-10-08 20:38:39 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	5b3c415c6f	debugging refactoring; fixed up embed.html; started DASM macro parse; Z80 stack view; replay wraps buffer > 120 secs; verilog edits	2018-08-25 13:50:18 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	6e5005f613	look in cache first, fetch local/ verilog includes too; apple2 reset; platform checkmark	2018-07-25 13:02:44 -04:00
Steven Hugg	4ea23e21f2	fixed verilog local paths	2018-07-22 22:26:03 -04:00
Steven Hugg	0ee201b9e8	update presets; redir.html expire	2018-06-01 10:33:37 -07:00
Steven Hugg	8f1563f88e	sync vs async RAM	2018-02-28 09:26:37 -06:00
Steven Hugg	b5c74234f3	smoother scope transition; slowest/fastest buttons; video width tweak	2018-02-27 14:09:27 -06:00
Steven Hugg	73bb496511	pixel editor takes 8'hxx format; fixed minor bugs	2018-02-26 15:55:39 -06:00