6 Commits

Author	SHA1	Message	Date
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	d5a146bf71	update lsfr preset; filter verilog boring errors	2018-07-21 09:34:06 -05:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00
Steven Hugg	89b1c64ac8	minor changes; preset changes; rotate output	2018-02-14 13:38:50 -06:00