7 Commits

Author	SHA1	Message	Date
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	f466afa085	updated cpu_platform.v to have inputs	2018-07-11 19:53:05 -07:00
Steven Hugg	e29bfb5f7e	working on assembler	2018-05-27 11:13:06 -07:00
Steven Hugg	c14e470778	can load verilog module from .asm file	2018-03-01 23:15:33 -06:00
Steven Hugg	725770ea3b	new presets	2018-03-01 20:17:37 -06:00
Steven Hugg	db005dc98e	can scroll scope when paused; updates to presets	2018-02-28 12:13:59 -06:00