10 Commits

Author	SHA1	Message	Date
Steven Hugg	63a5875283	verilog: added comments	2020-05-13 12:50:16 -05:00
Steven Hugg	706a24c96a	updated presets, changed array syntax, ice40 fpga examples	2018-10-08 20:38:39 -04:00
Steven Hugg	716205a2b1	fixed unit tests	2018-10-03 15:06:48 -04:00
Steven Hugg	684a642ad0	fixed multiplex issue in racing_game	2018-10-01 22:03:44 -04:00
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	bd8c4da2d6	verilog presets; early exit from jsasm errors	2018-09-08 19:14:51 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	2fce80bc9d	fixed asmlines in inline asm; reset h/vpaddle on vsync; fixed framebuffer.v	2018-07-17 22:17:01 -05:00
Steven Hugg	f6d320a05b	new inline verilog assembler	2018-02-18 11:14:04 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00