9 Commits

Author	SHA1	Message	Date
Steven Hugg	9bb79c318f	(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm	2021-06-30 18:07:55 -05:00
Steven Hugg	7441196b2e	no more BOM on download files	2018-12-08 10:15:02 -05:00
Steven Hugg	c6f2382f26	verilog: cpu16 updates; minor changes	2018-12-07 11:03:24 -05:00
Steven Hugg	bd8c4da2d6	verilog presets; early exit from jsasm errors	2018-09-08 19:14:51 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	8f1563f88e	sync vs async RAM	2018-02-28 09:26:37 -06:00
Steven Hugg	b2beb2670c	more Verilog code; inline asm for depends; fixed tank	2018-02-25 10:34:27 -06:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00