23 Commits

Author	SHA1	Message	Date
Steven Hugg	10d04f9114	verilog: randomizeOnReset = true except for unit tests (only <=32 bit values reset)	2021-07-09 15:21:41 -05:00
Steven Hugg	85932132d1	verilog: fixed $time for tests (timescale == msec)	2021-07-08 16:47:27 -05:00
Steven Hugg	42920337ec	verilog: fix optimization for tick2(), removed > 64 bit tests, stop tracing when $stop/$finish, +SignExt	2021-07-08 15:50:16 -05:00
Steven Hugg	b9a0de6cac	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
Steven Hugg	e703c16dfe	verilog: worker re-uses memory	2021-07-06 23:56:01 -05:00
Steven Hugg	5cf56f9d04	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
Steven Hugg	3ec69792b0	verilog: working on 64-bit, debug tree, fix 1-bit sound	2021-07-05 11:56:57 -05:00
Steven Hugg	854a6a2cdc	verilog: fixed wasm array views, compare test, loadROM async?	2021-07-03 11:29:11 -05:00
Steven Hugg	9bb79c318f	(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm	2021-06-30 18:07:55 -05:00
Steven Hugg	68f19fbf11	tests: createTestDOM() function	2020-07-27 08:20:17 -05:00
Steven Hugg	5516ca96b5	refactored into composite typescript project (multiple tsconfig.json files)	2019-10-26 10:38:21 -05:00
Steven Hugg	26a91fa038	>32-bit warning for verilog	2018-12-30 13:29:38 -06:00
Steven Hugg	b171def11a	fixed some tests	2018-10-11 11:23:19 -04:00
Steven Hugg	05f5b96256	verilog -> typescript, but why does loadState() make it slow with racing_game_cpu?	2018-08-29 13:27:24 -04:00
Steven Hugg	d8a98989f5	converted src/platform to typescript; stack debug view	2018-08-16 22:30:51 -04:00
Steven Hugg	6e5005f613	look in cache first, fetch local/ verilog includes too; apple2 reset; platform checkmark	2018-07-25 13:02:44 -04:00
Steven Hugg	a8c1ead244	more modules to typescript	2018-07-10 19:58:46 -05:00
Steven Hugg	bbe665bb03	fixed verilog tests	2018-07-09 21:00:05 -05:00
Steven Hugg	80588fcb31	verilog: scope updates, show js code, simple cpu	2017-11-28 20:38:48 -05:00
Steven Hugg	32a65a74e0	redir.html	2017-11-23 21:54:51 -05:00
Steven Hugg	1cace9d35c	more verilog unit tests; updated SDCC js/wasm	2017-11-23 19:16:54 -05:00
Steven Hugg	aad8efcfec	added more verilog test cases	2017-11-22 16:51:21 -05:00
Steven Hugg	73e908256e	started adding verilog regress tests	2017-11-22 09:44:57 -05:00