24 Commits

Author	SHA1	Message	Date
Steven Hugg	bd00d98b77	split workermain into tools/* modules; share parseXMLPoorly()	2021-08-12 13:51:10 -05:00
Steven Hugg	4506ebd7e0	started migration to esbuild modules	2021-08-02 08:32:46 -05:00
Steven Hugg	f634007e51	verilog: genModuleSync (for testing)	2021-07-24 09:40:55 -05:00
Steven Hugg	bb818c34f8	verilog: fixed silice <ccast> case	2021-07-22 09:28:30 -05:00
Steven Hugg	ff4bbaccdb	verilog: added signed property to data types	2021-07-15 11:41:41 -05:00
Steven Hugg	8d756ff363	updated package-lock.json, define __MAIN__ and __8BITWORKSHOP__ for ca65	2021-07-15 11:10:37 -05:00
Steven Hugg	2fba433f7a	verilog: fixed reset values	2021-07-11 13:41:20 -05:00
Steven Hugg	10d04f9114	verilog: randomizeOnReset = true except for unit tests (only <=32 bit values reset)	2021-07-09 15:21:41 -05:00
Steven Hugg	876d66e6de	verilog: fixed video sync for vga mode; ignore line # changes	2021-07-09 12:56:26 -05:00
Steven Hugg	631b7c73a7	verilog: changed Proxy to Object.defineProperty()	2021-07-08 17:46:18 -05:00
Steven Hugg	85932132d1	verilog: fixed $time for tests (timescale == msec)	2021-07-08 16:47:27 -05:00
Steven Hugg	42920337ec	verilog: fix optimization for tick2(), removed > 64 bit tests, stop tracing when $stop/$finish, +SignExt	2021-07-08 15:50:16 -05:00
Steven Hugg	5ab0e397d3	verilog: fixed 64-bit casting, constant issues	2021-07-08 13:00:44 -05:00
Steven Hugg	6ac29d78dc	add binaryen.js to lib/	2021-07-07 20:37:46 -05:00
Steven Hugg	b9a0de6cac	verilog: test updates, source locations, labels, Silice	2021-07-07 15:43:35 -05:00
Steven Hugg	e703c16dfe	verilog: worker re-uses memory	2021-07-06 23:56:01 -05:00
Steven Hugg	5cf56f9d04	verilog: sort var defs, fix video sync	2021-07-06 22:26:29 -05:00
Steven Hugg	1ab0d290f8	verilog: fuzzhdl	2021-07-06 15:18:17 -05:00
Steven Hugg	bc13614b6a	verilog: $readmem, fixed while loop	2021-07-05 18:55:06 -05:00
Steven Hugg	3ec69792b0	verilog: working on 64-bit, debug tree, fix 1-bit sound	2021-07-05 11:56:57 -05:00
Steven Hugg	854a6a2cdc	verilog: fixed wasm array views, compare test, loadROM async?	2021-07-03 11:29:11 -05:00
Steven Hugg	c0d60edbad	verilog: refactor, trace buffer, fast video update	2021-07-03 09:03:12 -05:00
Steven Hugg	4e97cd2eef	verilog: wasm, HDLModuleRunner interface	2021-07-01 18:55:28 -05:00
Steven Hugg	9bb79c318f	(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm	2021-06-30 18:07:55 -05:00