13 Commits

Author	SHA1	Message	Date
Steven Hugg	5516ca96b5	refactored into composite typescript project (multiple tsconfig.json files)	2019-10-26 10:38:21 -05:00
Steven Hugg	26a91fa038	>32-bit warning for verilog	2018-12-30 13:29:38 -06:00
Steven Hugg	b171def11a	fixed some tests	2018-10-11 11:23:19 -04:00
Steven Hugg	05f5b96256	verilog -> typescript, but why does loadState() make it slow with racing_game_cpu?	2018-08-29 13:27:24 -04:00
Steven Hugg	d8a98989f5	converted src/platform to typescript; stack debug view	2018-08-16 22:30:51 -04:00
Steven Hugg	6e5005f613	look in cache first, fetch local/ verilog includes too; apple2 reset; platform checkmark	2018-07-25 13:02:44 -04:00
Steven Hugg	a8c1ead244	more modules to typescript	2018-07-10 19:58:46 -05:00
Steven Hugg	bbe665bb03	fixed verilog tests	2018-07-09 21:00:05 -05:00
Steven Hugg	80588fcb31	verilog: scope updates, show js code, simple cpu	2017-11-28 20:38:48 -05:00
Steven Hugg	32a65a74e0	redir.html	2017-11-23 21:54:51 -05:00
Steven Hugg	1cace9d35c	more verilog unit tests; updated SDCC js/wasm	2017-11-23 19:16:54 -05:00
Steven Hugg	aad8efcfec	added more verilog test cases	2017-11-22 16:51:21 -05:00
Steven Hugg	73e908256e	started adding verilog regress tests	2017-11-22 09:44:57 -05:00