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85 lines
1.8 KiB
Verilog
85 lines
1.8 KiB
Verilog
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`include "hvsync_generator.v"
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`include "digits10.v"
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`include "ram.v"
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/*
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Displays a grid of digits on the CRT using a RAM module.
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*/
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module test_ram1_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [2:0] rgb;
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wire display_on;
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wire [9:0] hpos;
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wire [9:0] vpos;
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wire [9:0] ram_addr;
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wire [7:0] ram_read;
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reg [7:0] ram_write;
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reg ram_writeenable = 0;
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// RAM to hold 32x32 array of bytes
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RAM_sync ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(ram_addr),
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.we(ram_writeenable)
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);
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [4:0] row = vpos[7:3]; // 5-bit row, vpos / 8
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wire [4:0] col = hpos[7:3]; // 5-bit column, hpos / 8
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wire [2:0] rom_yofs = vpos[2:0]; // scanline of cell
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wire [4:0] rom_bits; // 5 pixels per scanline
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wire [3:0] digit = ram_read[3:0]; // read digit from RAM
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wire [2:0] xofs = hpos[2:0]; // which pixel to draw (0-7)
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assign ram_addr = {row,col}; // 10-bit RAM address
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// digits ROM
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digits10_case numbers(
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.digit(digit),
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.yofs(rom_yofs),
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.bits(rom_bits)
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);
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// extract bit from ROM output
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wire r = display_on && 0;
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wire g = display_on && rom_bits[~xofs];
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wire b = display_on && 0;
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assign rgb = {b,g,r};
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// increment the current RAM cell
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always @(posedge clk)
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case (hpos[2:0])
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// on 7th pixel of cell
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6: begin
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// increment RAM cell
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ram_write <= (ram_read + 1);
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// only enable write on last scanline of cell
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ram_writeenable <= (vpos[2:0] == 7);
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end
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// on 8th pixel of cell
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7: begin
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// disable write
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ram_writeenable <= 0;
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end
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endcase
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endmodule
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