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179 lines
4.7 KiB
Verilog
179 lines
4.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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//
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// --------------------------------------------------------
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// Bug Description:
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//
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// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
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// input to the flop does not propagate to the output
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// signal entry_vld[0] correctly. The value that propagates
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// is the new value of dvld[0] not the one just before the
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// posedge of gclk_vld[0].
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// --------------------------------------------------------
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// Define to see the bug with test failing with gated clock 'gclk_vld'
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// Comment out the define to see the test passing with ungated clock 'clk'
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`define GATED_CLK_TESTCASE 1
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// A side effect of the problem is this warning, disabled by default
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//verilator lint_on IMPERFECTSCH
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// Test Bench
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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// Take CRC data and apply to testblock inputs
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wire [7:0] dvld = crc[7:0];
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wire [7:0] ff_en_e1 = crc[15:8];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] entry_vld; // From test of Test.v
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wire [7:0] ff_en_vld; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.ff_en_vld (ff_en_vld[7:0]),
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.entry_vld (entry_vld[7:0]),
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// Inputs
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.clk (clk),
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.dvld (dvld[7:0]),
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.ff_en_e1 (ff_en_e1[7:0]));
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reg err_code;
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reg ffq_clk_active;
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reg [7:0] prv_dvld;
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initial begin
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err_code = 0;
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ffq_clk_active = 0;
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end
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always @ (posedge clk) begin
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prv_dvld = test.dvld;
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end
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always @ (negedge test.ff_entry_dvld_0.clk) begin
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ffq_clk_active = 1;
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if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
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$display(" en=%b fen=%b d=%b ev=%b",
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test.flop_en_vld[0], test.ff_en_vld[0],
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test.dvld[0], test.entry_vld[0]);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc<3) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
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if (ffq_clk_active == 0) begin
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$display ("----");
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$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
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$display ("----");
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$stop;
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end
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else if (err_code) begin
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$display ("----");
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$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
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$display ("----");
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$stop;
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end
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else begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module llq (clk, d, q);
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parameter WIDTH = 32;
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input clk;
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input [WIDTH-1:0] d;
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output [WIDTH-1:0] q;
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reg [WIDTH-1:0] qr;
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/* verilator lint_off COMBDLY */
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always @(clk or d)
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if (clk == 1'b0)
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qr <= d;
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/* verilator lint_on COMBDLY */
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assign q = qr;
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endmodule
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module ffq (clk, d, q);
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parameter WIDTH = 32;
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input clk;
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input [WIDTH-1:0] d;
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output [WIDTH-1:0] q;
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reg [WIDTH-1:0] qr;
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always @(posedge clk)
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qr <= d;
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assign q = qr;
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endmodule
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// DUT module
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module Test (/*AUTOARG*/
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// Outputs
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ff_en_vld, entry_vld,
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// Inputs
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clk, dvld, ff_en_e1
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);
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input clk;
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input [7:0] dvld;
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input [7:0] ff_en_e1;
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output [7:0] ff_en_vld;
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output wire [7:0] entry_vld;
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wire [7:0] gclk_vld;
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wire [7:0] ff_en_vld /*verilator clock_enable*/;
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reg [7:0] flop_en_vld;
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always @(posedge clk) flop_en_vld <= ff_en_e1;
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// clock gating
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`ifdef GATED_CLK_TESTCASE
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assign gclk_vld = {8{clk}} & ff_en_vld;
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`else
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assign gclk_vld = {8{clk}};
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`endif
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// latch for avoiding glitch on the clock gating control
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llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
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// flops that use the gated clock signal
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ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
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ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
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ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
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ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
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ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
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ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
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ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
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ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
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endmodule
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