Steven Hugg 48baf73ecb variable inspection, bitmaps for verilog, active high hsync/vsync, powerup vs reset

2017-11-21 14:12:02 -05:00

..

ball_paddle.v

start yosys profiling

2017-11-20 10:32:34 -05:00

clock_divider.v

support `include statements in verilog; book link changes; paddle/switches; scope transitions

2017-11-16 10:30:47 -05:00

digits10.v

variable inspection, bitmaps for verilog, active high hsync/vsync, powerup vs reset

2017-11-21 14:12:02 -05:00

hvsync_generator.v

variable inspection, bitmaps for verilog, active high hsync/vsync, powerup vs reset

2017-11-21 14:12:02 -05:00

lfsr.v

support `include statements in verilog; book link changes; paddle/switches; scope transitions

2017-11-16 10:30:47 -05:00

pong.v

support `include statements in verilog; book link changes; paddle/switches; scope transitions

2017-11-16 10:30:47 -05:00

skeleton.verilator

start yosys profiling

2017-11-20 10:32:34 -05:00

test_hvsync.v

more paddle/pong stuff; wider compiler msgs

2017-11-17 17:03:11 -05:00