6502/8bitworkshop
1
0
Fork 0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-11-25 03:34:05 +00:00
Code Issues Projects Releases Wiki Activity
5ab0e397d3
8bitworkshop/test/cli/verilog
History
Steven Hugg 5ab0e397d3 verilog: fixed 64-bit casting, constant issues
2021-07-08 13:00:44 -05:00
..
darksocv.v add binaryen.js to lib/ 2021-07-07 20:37:46 -05:00
t_alw_combdly.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_alw_dly.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_alw_nosplit.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_alw_reorder.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_alw_split_rst.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_alw_split.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_alw_splitord.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_array_compare.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_assert_basic.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_casez.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_comp.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_cover.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_disable_iff.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_elab.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_implication.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_on.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_property.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_question.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assert_synth.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_assign_inline.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_attr_parenstar.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_bitsel_enum.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_bitsel_slice.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_blocking.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_deep.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_dupitems.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_group.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_huge_sub3.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_case_itemwidth.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_onehot.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_orig.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_reducer.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_case_x.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_cellarray.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_chg_first.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_clk_2in.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_condflop_nord.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_condflop.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_dpulse.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_dsp.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_first.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_gate_ext.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_clk_gen.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_latch.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_latchgate.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clk_powerdn.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_clocker.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_concat_large.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_concat_opt.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_concat_sel.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_const.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_crazy_sel.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_EXAMPLE.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_fork_bbox.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_fork_label.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_endian.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_first.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_flip.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_gen.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_grey.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_lib.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_mlog2.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_numones.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_outfirst.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_outp.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_paramed.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_plog.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_range.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_real_param.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_regfirst.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_under2.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_under.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_uninit.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_func_wide.v verilog: sort var defs, fix video sync 2021-07-06 22:26:29 -05:00
t_gate_elim.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gate_lvalue_const.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gated_clk_1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_alw.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_gen_cond_bitrange.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_cond_const.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_div0.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for0.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for_interface.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for_overlap.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for_shuffle.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_for.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_inc.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_index.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_intdot2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_gen_local.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inside_wild.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_dff.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_mism.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_missing.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_mnpipe.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_port_array.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_prepost.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_signed1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_signed.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_slice_part_select.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_slice.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_inst_tree.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface1_modport.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_ar2a.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_ar2b.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_gen4.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_gen5.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_gen6.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_gen12.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_gen.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_modport_import.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_modportlist.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_param1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_parameter_access.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_interface_twod.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_langext_1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_langext_2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_langext_3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_arith.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_math_cmp.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_concat0.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_concat64.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_concat.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_cond_clean.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_const.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_math_div.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_math_divw.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_math_eq.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_equal.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_imm2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_imm.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_msvc_64.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_mul.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_pick.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_real_public.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_red.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_repl.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_reverse.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_shift_extend.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_shift_rep.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_shift_sel.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_shift.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_shiftrs.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_sign_extend.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed4.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed6.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed7.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_signed_wire.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_strwidth.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_svl2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_swap.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_tri.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_vliw.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_width.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_math_yosys.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_banks.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_cond.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_fifo.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_func.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_iforder.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_multi_io2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_multi_io.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_multidim.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_packed_assign.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_packed.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_shift.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_slice.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_slot.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem_twoedge.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mem.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_mod_dup_ign.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mod_interface_array0.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mod_interface_array1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mod_interface_array2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mod_recurse1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_mod_uselib.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_multitop1s.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_multitop_sig.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_no_sel_assign_merge_in_cpp.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_opt_table_enum.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_opt_table_packed_array.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_opt_table_same.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_opt_table_signed.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_opt_table_sparse.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_optm_if_array.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_optm_if_cond.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_optm_redor.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_order_2d.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_a.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_b.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_clkinst.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_comboclkloop.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_comboloop.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_doubleloop.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_first.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_multialways.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_multidriven.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_quad.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_order_wireloop.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_param_array2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_array3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_array4.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_array5.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_array.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_avec.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_bit_sel.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_bracket.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_ceil.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_chain.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_const_part.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_ddeep_width.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_default.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_first_b.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_func2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_func.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_if_blk.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_local.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_mem_attr.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_module.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_no_parentheses.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_package.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_real2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_real.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_repl.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_seg.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_sel.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_shift.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_type2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_type3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_type.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_unreachable.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_value.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_while.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_wide_io.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param_width.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_param.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_parse_delay.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_past_funcs.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_past.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_pp_display.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_pp_pragmas.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_real_param.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_reloop_offset.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_rnd.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_runflag.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_sc_names.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_2d.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_bound1.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_bound2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_index2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_index.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_lhs_oob2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_lhs_oob.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_little_pack.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_little.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_param.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_plus_mul_pow2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_runtime_range.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_select_set.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_slice_cond.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_slice_init.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_static_elab.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_table_fsm.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_time_literals.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_array_bufif.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_array_pull.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_eqcase.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_gen.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_graph.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_ifbegin.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_inout2.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_inout.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_inz.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_pull01.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_pullup.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_select_unsized.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_select.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_tri_unconn.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_tri_various.v (WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm 2021-06-30 18:07:55 -05:00
t_type_param.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_type.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unbounded.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unconnected.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_uniqueif.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unopt_array.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unopt_combo.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unopt_converge_initial.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unopt_converge.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unoptflat_simple_2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unoptflat_simple_3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unoptflat_simple.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unpacked_slice.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unroll_forfor.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_unroll_genf.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_vams_basic.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_assign_landr.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_const.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_dup2.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_dup3.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_in_assign.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_init.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_life.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_local.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_nonamebegin.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_overcmp.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_overzero.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_pinsizes.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_set_link.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_tieout.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_types.v verilog: fixed 64-bit casting, constant issues 2021-07-08 13:00:44 -05:00
t_var_vec_sel.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_var_xref_gen.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_waiveroutput.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_wire_types.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00
t_x_assign.v verilog: test updates, source locations, labels, Silice 2021-07-07 15:43:35 -05:00