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101 lines
3.0 KiB
Verilog
101 lines
3.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off LITENDIAN
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// verilator lint_off BLKANDNBLK
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// 3 3 4
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reg [71:0] memw [2:0][1:3][5:2];
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reg [7:0] memn [2:0][1:3][5:2];
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// verilator lint_on BLKANDNBLK
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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reg [71:0] wide;
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reg [7:0] narrow;
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reg [1:0] index0;
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reg [1:0] index1;
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reg [2:0] index2;
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integer i0,i1,i2;
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integer imem[2:0][1:3];
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reg [2:0] cstyle[2];
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// verilator lint_on LITENDIAN
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initial begin
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for (i0=0; i0<3; i0=i0+1) begin
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for (i1=1; i1<4; i1=i1+1) begin
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imem[i0[1:0]] [i1[1:0]] = i1;
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for (i2=2; i2<6; i2=i2+1) begin
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memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]};
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memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001;
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end
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end
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end
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end
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reg [71:0] wread;
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reg wreadb;
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always @ (posedge clk) begin
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//$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide);
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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narrow <= 8'h0;
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wide <= 72'h0;
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index0 <= 2'b0;
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index1 <= 2'b0;
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index2 <= 3'b0;
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end
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else if (cyc<90) begin
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index0 <= crc[1:0];
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index1 <= crc[3:2];
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index2 <= crc[6:4];
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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// We never read past bounds, or get unspecific results
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// We also never read lowest indexes, as writing outside of range may corrupt them
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if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin
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narrow <= ({narrow[6:0], narrow[7]^narrow[0]}
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^ {memn[index0][index1][index2]});
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wread = memw[index0][index1][index2];
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wreadb = memw[index0][index1][index2][2];
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wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread);
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//$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread);
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end
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// We may write past bounds of memory
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memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0];
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memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
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memw[index0][index1][index2] <= {~crc[7:0],crc};
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//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
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cstyle[cyc[0]] <= cyc[2:0];
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if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop;
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end
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else if (cyc==90) begin
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memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
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end
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else if (cyc==91) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide);
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if (crc != 64'h65e3bddcd9bc2750) $stop;
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if (narrow != 8'hca) $stop;
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if (wide != 72'h4edafed31ba6873f73) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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