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web-based IDE for 8-bit programming and Verilog development
367 Commits 3 Branches 31 Tags 162 MiB
JavaScript 52.5%
TypeScript 16.9%
C 16.1%
Verilog 5.8%
Assembly 5%
Other 3.6%
8ad8d0e88c
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Steven Hugg 8ad8d0e88c signal names on top, remove clk/reset from video, wave numbers at high zoom
2018-09-12 20:38:52 -04:00
bootstrap
cc65
codemirror@4334727f0e
css new scope module for verilog 2018-09-12 11:50:21 -04:00
doc new scope module for verilog 2018-09-12 11:50:21 -04:00
emsrc
FileSaver.js@aa9f4e0e03
gif.js@082076d81c
images
javatari.js@bd17384fd2
jquery
jsnes
lib signal names on top, remove clk/reset from video, wave numbers at high zoom 2018-09-12 20:38:52 -04:00
localForage@7428cfc4a6
mame
octokat.js@2cba2d9172
presets minor stuff 2018-09-11 09:04:03 -04:00
romsrc/coleco
scripts
src signal names on top, remove clk/reset from video, wave numbers at high zoom 2018-09-12 20:38:52 -04:00
test fixed tests, printFlags, debug info 2018-08-29 23:44:17 -04:00
tools added error alerts; fixed window list; fixed z80 stack; astrocade .c bios 2018-09-05 09:31:57 -04:00
tss@d630ddcb29
_config.yml
.gitignore
.gitmodules added font generator to menu, added submodules 2018-09-02 17:03:17 -04:00
.htaccess
.travis.yml
demo.html
embed.html
favicon.ico
index.html new scope module for verilog 2018-09-12 11:50:21 -04:00
javatari
LICENSE
Makefile
package-lock.json more work on font generator 2018-09-02 09:52:00 -04:00
package.json more work on font generator 2018-09-02 09:52:00 -04:00
pixels.html
privacy.html
README.md
redir.html
testemu.html
testwave.html new scope module for verilog 2018-09-12 11:50:21 -04:00
tsconfig.json

README.md

8bitworkshop

8bitworkshop.com

git submodule init
git submodule update
npm i
npm run build