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97 lines
2.8 KiB
Verilog
97 lines
2.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [255:0] a;
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reg [60:0] divisor;
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reg [60:0] qq;
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reg [60:0] rq;
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reg signed [60:0] qqs;
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reg signed [60:0] rqs;
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always @* begin
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qq = a[60:0] / divisor;
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rq = a[60:0] % divisor;
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qqs = $signed(a[60:0]) / $signed(divisor);
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rqs = $signed(a[60:0]) % $signed(divisor);
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
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if (cyc==1) begin
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a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
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divisor <= 61'h12371;
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a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
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end
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if (cyc==2) begin
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a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
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divisor <= 61'h1238123771;
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a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
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if (qq!==61'h00000403ad81c0da) $stop;
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if (rq!==61'h00000000000090ec) $stop;
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if (qqs!==61'h00000403ad81c0da) $stop;
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if (rqs!==61'h00000000000090ec) $stop;
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end
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if (cyc==3) begin
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a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
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divisor <= 61'hf1b;
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a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
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if (qq!==61'h000000000090832e) $stop;
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if (rq!==61'h0000000334becc6a) $stop;
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if (qqs!==61'h000000000090832e) $stop;
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if (rqs!==61'h0000000334becc6a) $stop;
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end
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if (cyc==4) begin
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a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
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if (qq!==61'h0001eda37cca1be8) $stop;
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if (rq!==61'h0000000000000c40) $stop;
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if (qqs!==61'h1fffcf5187c76510) $stop;
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if (rqs!==61'h1ffffffffffffd08) $stop;
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end
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if (cyc==5) begin
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a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
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if (qq!==61'h0000000000000000) $stop;
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if (rq!==61'h0d20a48e00f395b8) $stop;
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if (qqs!==61'h0000000000000000) $stop;
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if (rqs!==61'h0d20a48e00f395b8) $stop;
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end
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if (cyc==6) begin
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if (qq!==61'h0000000000000001) $stop;
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if (rq!==61'h0d20a48e00f3869d) $stop;
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if (qqs!==61'h0000000000000000) $stop;
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if (rqs!==61'h1d20a48e00f395b8) $stop;
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end
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// Div by zero
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if (cyc==9) begin
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divisor <= 61'd0;
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end
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if (cyc==10) begin
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`ifdef verilator
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if (qq !== {61{1'b0}}) $stop;
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if (rq !== {61{1'b0}}) $stop;
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`else
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if (qq !== {61{1'bx}}) $stop;
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if (rq !== {61{1'bx}}) $stop;
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`endif
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if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
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if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
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end
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if (cyc==19) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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