mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-27 01:51:35 +00:00
12 lines
201 B
Verilog
12 lines
201 B
Verilog
module t(y);
|
|
output [3:0] y;
|
|
// bug775
|
|
// verilator lint_off WIDTH
|
|
assign y = ((0/0) ? 1 : 2) % 0;
|
|
|
|
initial begin
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|