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31 lines
491 B
Verilog
31 lines
491 B
Verilog
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/*
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A clock divider in Verilog, using the cascading
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flip-flop method.
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*/
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module clock_divider(
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input clk,
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input reset,
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output reg clk_div2,
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output reg clk_div4,
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output reg clk_div8,
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output reg clk_div16
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);
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// simple ripple clock divider
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always @(posedge clk)
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clk_div2 <= ~clk_div2;
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always @(posedge clk_div2)
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clk_div4 <= ~clk_div4;
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always @(posedge clk_div4)
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clk_div8 <= ~clk_div8;
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always @(posedge clk_div8)
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clk_div16 <= ~clk_div16;
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endmodule
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