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Steven Hugg ca0c7cf045 verilog.sim platform and verilog.html

2018-11-18 12:30:41 -05:00

bootstrap

added base_z80 platform and viz.html example

2017-04-29 11:53:27 -04:00

cc65

added cc65, asm/link to wasm, new timer funcs

2017-11-07 18:15:29 -05:00

codemirror @ 4334727f0e

updated presets; verilog code dup detect; need to handle local/ include files somehow

2018-07-31 23:03:53 -04:00

css

3.2.0

2018-10-03 14:35:26 -04:00

doc

Merge branch 'master' of github.com:sehugg/8bitworkshop

2018-11-15 20:01:15 -05:00

emsrc

caspr inline assembly with __asm

2018-02-15 09:56:45 -06:00

FileSaver.js @ aa9f4e0e03

download ROM image

2017-02-02 14:11:52 -05:00

gif.js @ 082076d81c

better video recording (rotate, copy frames); preset updates

2017-06-21 10:32:42 -04:00

images

can't resume before ROM build; added verilog to demo.html

2018-11-15 20:01:02 -05:00

javatari.js @ bd17384fd2

finished zmac asm (.z); fixed javatari submodule tag; upgraded tsc

2018-08-28 15:42:56 -04:00

jquery

initial commit

2016-12-15 20:21:51 -05:00

jsnes

started on JSNES support

2018-07-28 09:46:27 -04:00

lib

apple2 cassette export w/ c2t

2018-09-25 19:46:24 -04:00

localForage @ 7428cfc4a6

use localForage for file store

2018-06-26 02:56:36 -04:00

mame

added atari5200 support; fixed NES presets

2018-06-23 18:59:36 -04:00

octokat.js @ 2cba2d9172

use Github gists for sharing

2017-01-25 12:30:05 -05:00

presets

moved fpga examples to https://github.com/sehugg/fpga-examples ; new framebuffer.v

2018-11-12 14:13:17 -05:00

romsrc/coleco

added CV alt. rom to romsrc/

2017-11-10 11:16:28 -05:00

scripts

inspect variables by selecting

2018-08-27 12:38:55 -04:00

src

verilog.sim platform and verilog.html

2018-11-18 12:30:41 -05:00

test

fixed some tests

2018-10-11 11:23:19 -04:00

tools

added error alerts; fixed window list; fixed z80 stack; astrocade .c bios

2018-09-05 09:31:57 -04:00

tss @ d630ddcb29

AY38910_Audio

2017-01-28 13:49:56 -05:00

_config.yml

Set theme jekyll-theme-cayman

2018-03-01 10:50:56 -06:00

.gitignore

added scripts

2018-07-26 08:50:20 -07:00

.gitmodules

added font generator to menu, added submodules

2018-09-02 17:03:17 -04:00

.htaccess

better error reporting in timer callback; .htaccess for redir.html cache

2018-08-25 21:38:15 -04:00

.travis.yml

converting some stuff to TypeScript (make tsweb)

2018-07-05 21:23:08 -05:00

demo.html

can't resume before ROM build; added verilog to demo.html

2018-11-15 20:01:02 -05:00

embed.html

debugging refactoring; fixed up embed.html; started DASM macro parse; Z80 stack view; replay wraps buffer > 120 secs; verilog edits

2018-08-25 13:50:18 -04:00

favicon.ico

no splash screen when sharekey present

2017-04-28 08:32:05 -04:00

index.html

added platform verilog to menu; fixed for TS 3.1

2018-10-11 11:43:09 -04:00

javatari

initial commit

2016-12-15 20:21:51 -05:00

LICENSE

Initial commit

2016-12-15 19:56:58 -05:00

LICENSE.txt

updated comments for all vcs examples

2018-09-30 21:07:45 -04:00

Makefile

verilog.sim platform and verilog.html

2018-11-18 12:30:41 -05:00

package-lock.json

fix unit tests

2018-10-03 21:14:10 -04:00

package.json

added platform verilog to menu; fixed for TS 3.1

2018-10-11 11:43:09 -04:00

pixels.html

if you work hard and follow your dreams, you too can center <div>s vertically

2018-08-21 09:27:14 -04:00

privacy.html

website privacy policy

2018-08-01 18:18:47 -04:00

README.md

added scripts

2018-07-26 08:50:20 -07:00

redir.html

3.2.0

2018-10-03 14:35:26 -04:00

testemu.html

updated nes presets

2018-07-28 11:01:38 -04:00

testwave.html

new global kbd shortcuts; vcs show bank offset; effective PC (c.EPC) for bankswitching debugging

2018-09-13 21:34:04 -04:00

tsconfig.json

don't use WASM for Node tests until we get memory errors fixed

2018-07-10 18:02:29 -05:00

verilog.html

verilog.sim platform and verilog.html

2018-11-18 12:30:41 -05:00

README.md

8bitworkshop

8bitworkshop.com

git submodule init
git submodule update
npm i
npm run build

Languages

JavaScript 49.9%

TypeScript 18.7%

C 16.5%

Verilog 5.9%

Assembly 4.9%

Other 3.9%