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123 lines
3.1 KiB
Verilog
123 lines
3.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg reset_l;
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// verilator lint_off GENCLK
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// End of automatics
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reg clkgate_e2r;
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reg clkgate_e1r_l;
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always @(posedge clk or negedge reset_l) begin
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if (!reset_l) begin
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clkgate_e1r_l <= ~1'b1;
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end
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else begin
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clkgate_e1r_l <= ~clkgate_e2r;
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end
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end
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reg clkgate_e1f;
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always @(negedge clk) begin
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// Yes, it's really a =
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clkgate_e1f = ~clkgate_e1r_l | ~reset_l;
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end
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wire clkgated = clk & clkgate_e1f;
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reg [31:0] countgated;
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always @(posedge clkgated or negedge reset_l) begin
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if (!reset_l) begin
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countgated <= 32'h1000;
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end
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else begin
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countgated <= countgated + 32'd1;
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end
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end
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reg [31:0] count;
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always @(posedge clk or negedge reset_l) begin
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if (!reset_l) begin
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count <= 32'h1000;
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end
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else begin
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count <= count + 32'd1;
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end
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end
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reg [7:0] cyc; initial cyc=0;
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n",$time,reset_l,cyc,clkgate_e1f,count,countgated);
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`endif
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cyc <= cyc + 8'd1;
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case (cyc)
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8'd00: begin
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reset_l <= ~1'b0;
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clkgate_e2r <= 1'b1;
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end
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8'd01: begin
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reset_l <= ~1'b0;
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end
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8'd02: begin
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end
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8'd03: begin
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reset_l <= ~1'b1; // Need a posedge
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end
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8'd04: begin
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end
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8'd05: begin
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reset_l <= ~1'b0;
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end
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8'd09: begin
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clkgate_e2r <= 1'b0;
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end
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8'd11: begin
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clkgate_e2r <= 1'b1;
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end
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8'd20: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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case (cyc)
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8'd00: ;
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8'd01: ;
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8'd02: ;
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8'd03: ;
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8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
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8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
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8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop;
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8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop;
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8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop;
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8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop;
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8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop;
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8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop;
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8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop;
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8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop;
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8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop;
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8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop;
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8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop;
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8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop;
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8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop;
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8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop;
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8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop;
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default: $stop;
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endcase
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end
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endmodule
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