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AtomBusMon/target/lx9_dave/icez80/memory.bmm

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Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
ADDRESS_MAP avrmap PPC405 0
lx9_dave z80: increase code space to 32KB Change-Id: I7ab22f8cca51184b94e709336b661b8685d02d0b
2019-10-25 17:11:13 +01:00
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00007fff]
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
BUS_BLOCK
Updated lx9_dave/icez80 for active level shifter design Change-Id: I546e1afc0943443f444ae7f55783bac7e3379453
2019-09-20 15:34:34 +01:00
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_BUS_BLOCK;
lx9_dave z80: increase code space to 32KB Change-Id: I7ab22f8cca51184b94e709336b661b8685d02d0b
2019-10-25 17:11:13 +01:00
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[9].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[10].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[11].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[12].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[13].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[14].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/mon/Inst_AVR8/PM_Inst/RAM_Inst[15].Ram [15:0];
END_BUS_BLOCK;
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d
2018-11-20 09:34:27 +00:00
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
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