AtomBusMon/target/lx9_dave/ice6502/Makefile

# The root directory of the project
ROOT       = ../../..

# The common directory for makefile includes, etc.
COMMON     = ../../common

# The project .bit file produced by the Xilinx .xise project
PROJECT    = W65C02CpuMon

# The target .bit file to be generated including the monitor program
TARGET     = ice6502

# Frequuency that the AVR runs at
F_CPU      = 19354838

# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d 2018-11-20 09:34:27 +00:00			`# The root directory of the project`
			`ROOT = ../../..`

			`# The common directory for makefile includes, etc.`
			`COMMON = ../../common`

			`# The project .bit file produced by the Xilinx .xise project`
Updated lx9_dave/ice6502 with correct .ucf file and a new top-level design Change-Id: Ic67e37fb876322983a44c35e9db08b1b8371aea2 2018-11-20 17:32:02 +00:00			`PROJECT = W65C02CpuMon`
Checked in initial work on lx9_dave target (see full comment) The .ucf files look like they are for a completely different board (the lx9 starter board, not the epizza board). So these need to be reworked completely. Also, the following signals needs adding to the top level 6502 design: - OEAH (output) - OEAL (output) - OED (output) - ML (output) - VP (output) - BE (input) The system will not work without some attention to these. Minimally, in the FPGA design we can tie them as follows: - OEAH (output) - set to 0 (address bus always enabled) - OEAL (output) - set to 0 (ditto) - OED (output) - set to !phi2 (data bus driven in second half of clock) - ML (output) - set output to 1 (and fit P3 link between pins 2 and 3) - VP (output) - set output to 1 (and don't fit P4 link) - BE (input) - ignore input The current adapter design does not fully support the implementation of BE as it does not provide a way to tristate RNW. That would require the addition of a seperate level shifter, e.g. a 74LVC1G125 Change-Id: I1bf11c5ef8318c5ebfa942cb4bd07f750d0b370d 2018-11-20 09:34:27 +00:00
			`# The target .bit file to be generated including the monitor program`
			`TARGET = ice6502`

			`# Frequuency that the AVR runs at`
			`F_CPU = 19354838`

			`# Common include files`
			`include $(COMMON)/Makefile_$(TARGET).inc`
			`include $(COMMON)/Makefile.inc`