mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-03-11 14:35:35 +00:00
Updated lx9_dave/ice6502 with correct .ucf file and a new top-level design
Change-Id: Ic67e37fb876322983a44c35e9db08b1b8371aea2
This commit is contained in:
David Banks
parent
a277222012
commit
1dcf9fa247
168
src/W65C02CpuMon.vhd
Normal file
168
src/W65C02CpuMon.vhd
Normal file
@ -0,0 +1,168 @@
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--------------------------------------------------------------------------------
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-- Copyright (c) 2018 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : W65C02CpuMon.vhd
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-- /___/ /\ Timestamp : 20/11/2018
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: W65C02BusMon
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--Device: XC6SLX9
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--
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--
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-- This is a small wrapper around AtomCpuMon that add the following signals:
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-- OEAH_n
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-- OEAL_n
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-- OED_n
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-- BE
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-- ML_n
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-- VP_n
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-- (these are not fully implemented yet)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity W65C02CpuMon is
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false;
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LEDsActiveHigh : boolean := true; -- default value for EEPIZZA
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SW1ActiveHigh : boolean := true; -- default value for EEPIZZA
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SW2ActiveHigh : boolean := true; -- default value for EEPIZZA
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ClkMult : integer := 10; -- default value for EEPIZZA
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ClkDiv : integer := 31; -- default value for EEPIZZA
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ClkPer : real := 20.000 -- default value for EEPIZZA
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);
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port (
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clock49 : in std_logic;
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-- 6502 Signals
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : inout std_logic;
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Rdy : in std_logic;
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-- 65C02 Signals
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BE : in std_logic;
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ML_n : out std_logic;
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VP_n : out std_logic;
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-- Level Shifter Controls
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OEAH_n : out std_logic;
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OEAL_n : out std_logic;
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OED_n : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Jumpers
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fakeTube_n : in std_logic;
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw1 : in std_logic;
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sw2 : in std_logic;
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-- LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 LED display
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end W65C02CpuMon;
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architecture behavioral of W65C02CpuMon is
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signal R_W_n_int : std_logic;
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begin
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acm : entity work.AtomCpuMon
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore,
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LEDsActiveHigh => LEDsActiveHigh,
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SW1ActiveHigh => SW1ActiveHigh,
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SW2ActiveHigh => SW2ActiveHigh,
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ClkMult => ClkMult,
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ClkDiv => ClkDiv,
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ClkPer => ClkPer
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)
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port map (
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clock49 => clock49,
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-- 6502 Signals
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Phi0 => Phi0,
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Phi1 => Phi1,
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Phi2 => Phi2,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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Sync => Sync,
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Addr => Addr,
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R_W_n => R_W_n_int,
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Data => Data,
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SO_n => SO_n,
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Res_n => Res_n,
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Rdy => Rdy,
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-- External trigger inputs
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trig => trig,
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-- Jumpers
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fakeTube_n => fakeTube_n,
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-- Serial Console
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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-- Switches
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sw1 => sw1,
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sw2 => sw2,
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-- LEDs
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led3 => led3,
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led6 => led6,
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led8 => led8,
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-- OHO_DY1 LED display
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk
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);
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-- 6502 Outputs
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R_W_n <= R_W_n_int;
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-- 65C02 Outputs
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ML_n <= '1';
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VP_n <= '1';
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-- Level Shifter Controls
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OEAH_n <= not (BE);
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OEAL_n <= not (BE);
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OED_n <= not (BE or (Phi0 and not R_W_n_int)); -- TODO: might need to use a slightly delayed version of Phi0 here
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end behavioral;
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@ -5,7 +5,7 @@ ROOT = ../../..
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COMMON = ../../common
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# The project .bit file produced by the Xilinx .xise project
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PROJECT = AtomCpuMon
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PROJECT = W65C02CpuMon
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# The target .bit file to be generated including the monitor program
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TARGET = ice6502
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@ -6,73 +6,77 @@ TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW;
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NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "clock49" LOC="P21" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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NET "clock49" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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#NET "Rdy" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
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NET "Phi1" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
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NET "IRQ_n" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
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#NET "NC" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
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NET "NMI_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
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NET "Sync" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
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#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
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NET "Addr<0>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
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NET "Addr<1>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
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NET "Addr<2>" LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
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NET "Addr<3>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
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NET "Addr<4>" LOC="P50" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
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NET "Addr<5>" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
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NET "Addr<6>" LOC="P55" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
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NET "Addr<7>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
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NET "Addr<8>" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
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NET "Addr<9>" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
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NET "Addr<10>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
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NET "Addr<11>" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
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NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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#NET "Rdy" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
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NET "Phi1" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
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NET "IRQ_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
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NET "ML_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
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NET "NMI_n" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
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NET "Sync" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
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#NET "VCC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
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NET "Addr<0>" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
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NET "Addr<1>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
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NET "Addr<2>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
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NET "Addr<3>" LOC="P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
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NET "Addr<4>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
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NET "Addr<5>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
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NET "Addr<6>" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
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NET "Addr<7>" LOC="P14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
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NET "Addr<8>" LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
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NET "Addr<9>" LOC="P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
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NET "Addr<10>" LOC="P141" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
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NET "Addr<11>" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
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#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
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NET "Addr<12>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
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NET "Addr<13>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
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NET "Addr<14>" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
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NET "Addr<15>" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
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NET "Data<7>" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
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NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
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NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
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NET "Data<4>" LOC="P75" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
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NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
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NET "Data<2>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
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NET "Data<1>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
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NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
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NET "R_W_n" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
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#NET "NC" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
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NET "Phi0" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
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NET "SO_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
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NET "Phi2" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
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NET "Res_n" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
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#NET "VSS" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
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NET "Addr<12>" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
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NET "Addr<13>" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
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NET "Addr<14>" LOC="P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
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NET "Addr<15>" LOC="P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
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NET "Data<7>" LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
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NET "Data<6>" LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
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NET "Data<5>" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
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NET "Data<4>" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
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NET "Data<3>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
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NET "Data<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
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NET "Data<1>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
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NET "Data<0>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
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NET "R_W_n" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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#NET "NC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
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NET "BE" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
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NET "Phi0" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
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NET "SO_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
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NET "Phi2" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
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NET "Res_n" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
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# Level-shifter OE signals
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NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "OEAH_n" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "OED_n" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# LEDs and Switches
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NET "led3" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
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NET "led6" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
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NET "led8" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
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NET "sw1" LOC="P133" | IOSTANDARD = LVCMOS33 ; # reset
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NET "sw2" LOC="P132" | IOSTANDARD = LVCMOS33 ; # interrupt
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NET "led3" LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
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NET "led6" LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
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NET "led8" LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
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NET "sw1" LOC="P132" | IOSTANDARD = LVCMOS33 ; # reset
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NET "sw2" LOC="P131" | IOSTANDARD = LVCMOS33 ; # interrupt
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# 7-segment LED
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NET tmosi LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tdin LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tcclk LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tmosi LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# UART
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NET "avr_TxD" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "avr_RxD" LOC="P23" | IOSTANDARD = LVCMOS33 ;
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NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
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# External trigger inputs
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NET "trig<0>" LOC="P134" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P137" | IOSTANDARD = LVCMOS33 ;
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NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
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# Jumpers
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NET "fakeTube_n" LOC="P27" | IOSTANDARD = LVCMOS33 ;
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NET "fakeTube_n" LOC="P123" | IOSTANDARD = LVCMOS33 ;
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@ -257,6 +257,10 @@
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<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="../../../src/W65C02CpuMon.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
|
||||
</file>
|
||||
<file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
@ -380,9 +384,9 @@
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|W65C02CpuMon|behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/W65C02CpuMon.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/W65C02CpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -451,7 +455,7 @@
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@ -466,10 +470,10 @@
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="W65C02CpuMon_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="W65C02CpuMon_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="W65C02CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="W65C02CpuMon_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -493,7 +497,7 @@
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
|
||||
|
||||
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
|
||||
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
END_ADDRESS_SPACE;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user