mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-12-22 01:30:18 +00:00
Improved generate relaibility; increased from 4 to 8 watches/breakpoint addresses
Change-Id: I7ce5b1fbd259cd20c11555cf774bbba2fce43821
This commit is contained in:
David Banks
parent
c9c6001332
commit
015dbac541
@ -1,5 +1,6 @@
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#include <stdio.h>
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#include <string.h>
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#include <ctype.h>
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#include <avr/pgmspace.h>
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#include "hd44780.h"
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@ -73,7 +74,7 @@ char *modeStrings[7] = {
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#define VERSION "0.11"
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#define NUMCMDS 20
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#define MAXBKPTS 4
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#define MAXBKPTS 8
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int numbkpts = 0;
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@ -236,11 +237,12 @@ void logMode(unsigned int mode) {
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int first = 1;
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for (i = 0; i < UNDEFINED; i++) {
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if (mode & 1) {
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if (!first) {
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log0(",");
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first = 0;
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if (first) {
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log0("%s", modeStrings[i]);
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} else {
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log0(", %c%s", tolower(*modeStrings[i]), modeStrings[i] + 1);
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}
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log0("%s", modeStrings[i]);
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first = 0;
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}
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mode >>= 1;
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}
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@ -368,20 +370,17 @@ void doCmdBreak(char *params, unsigned int mode) {
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} else {
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setBreakpoint(i, addr, modes[i] | mode);
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}
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doCmdBList(NULL);
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return;
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}
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}
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if (numbkpts == MAXBKPTS) {
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log0("All breakpoints are already set\n");
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doCmdBList(NULL);
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log0("All %d breakpoints are already set\n", numbkpts);
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return;
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}
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numbkpts++;
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for (i = numbkpts - 2; i >= -1; i--) {
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if (i == -1 || breakpoints[i] < addr) {
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setBreakpoint(i + 1, addr, mode);
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doCmdBList(NULL);
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return;
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} else {
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breakpoints[i + 1] = breakpoints[i];
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@ -446,7 +445,6 @@ void doCmdBClear(char *params, unsigned int mode) {
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logMode(mode);
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log0(" not set at %04X\n", n);
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}
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doCmdBList(NULL);
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}
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void doCmdBClearI(char *params) {
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@ -487,7 +485,9 @@ void shiftBreakpointRegister(unsigned int addr, unsigned int mode) {
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void doCmdContinue(char *params) {
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int i;
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int status;
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doCmdBList(NULL);
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// Step the 6502, otherwise the breakpoint happends again immediately
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hwCmd(CMD_STEP, 0);
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// Disable breakpoints to allow loading
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hwCmd(CMD_BRKPT_ENABLE, 0);
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@ -520,6 +520,7 @@ void doCmdContinue(char *params) {
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doCmdAddr();
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cont = 0;
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}
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Delay_us(10);
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} while (cont);
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// Enable single stepping
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@ -542,8 +543,6 @@ void initialize() {
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hwCmd(CMD_RESET, 0);
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setSingle(1);
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setTrace(1);
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log0("6502 paused...\n");
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doCmdAddr();
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}
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void (*cmdFuncs[NUMCMDS])(char *params) = {
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@ -597,6 +596,7 @@ void dispatchCmd(char *cmd) {
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int main(void) {
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initialize();
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doCmdContinue(NULL);
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while (1) {
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readCmd(command);
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dispatchCmd(command);
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@ -17,11 +17,11 @@
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<files>
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<file xil_pn:name="WatchEvents.ngc" xil_pn:type="FILE_NGC">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="WatchEvents.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
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@ -29,341 +29,29 @@
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</files>
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<properties>
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<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
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<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
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<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
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<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
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<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
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<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
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<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
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<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
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<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
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<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
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<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
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<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|WatchEvents|WatchEvents_a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="WatchEvents.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/WatchEvents" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="WatchEvents" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="WatchEvents_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="WatchEvents_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="WatchEvents_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="WatchEvents_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="WatchEvents" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-10T19:17:46" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B14BB500359CAAA9F2FE2F4318B515B5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
|
||||
@ -23,79 +23,86 @@ use work.OhoPack.all ;
|
||||
|
||||
|
||||
entity AtomBusMon is
|
||||
port (clock49 : in std_logic;
|
||||
generic (
|
||||
num_comparators : integer := 8;
|
||||
reg_width : integer := 22;
|
||||
fifo_width : integer := 36
|
||||
);
|
||||
port (
|
||||
clock49 : in std_logic;
|
||||
|
||||
-- 6502 Signals
|
||||
Addr : in std_logic_vector(15 downto 0);
|
||||
Phi2 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
Sync : in std_logic;
|
||||
Rdy : out std_logic;
|
||||
nRST : inout std_logic;
|
||||
-- 6502 Signals
|
||||
Addr : in std_logic_vector(15 downto 0);
|
||||
Phi2 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
Sync : in std_logic;
|
||||
Rdy : out std_logic;
|
||||
nRST : inout std_logic;
|
||||
|
||||
-- HD44780 LCD
|
||||
lcd_rs : out std_logic;
|
||||
lcd_rw : out std_logic;
|
||||
lcd_e : out std_logic;
|
||||
lcd_db : inout std_logic_vector(7 downto 4);
|
||||
-- HD44780 LCD
|
||||
lcd_rs : out std_logic;
|
||||
lcd_rw : out std_logic;
|
||||
lcd_e : out std_logic;
|
||||
lcd_db : inout std_logic_vector(7 downto 4);
|
||||
|
||||
-- AVR Serial Port
|
||||
avr_RxD : in std_logic;
|
||||
avr_TxD : out std_logic;
|
||||
-- AVR Serial Port
|
||||
avr_RxD : in std_logic;
|
||||
avr_TxD : out std_logic;
|
||||
|
||||
-- GODIL Switches
|
||||
sw1 : in std_logic;
|
||||
nsw2 : in std_logic;
|
||||
-- GODIL Switches
|
||||
sw1 : in std_logic;
|
||||
nsw2 : in std_logic;
|
||||
|
||||
-- GODIL LEDs
|
||||
led3 : out std_logic;
|
||||
led6 : out std_logic;
|
||||
led8 : out std_logic;
|
||||
-- GODIL LEDs
|
||||
led3 : out std_logic;
|
||||
led6 : out std_logic;
|
||||
led8 : out std_logic;
|
||||
|
||||
-- OHO_DY1 connected to test connector
|
||||
tmosi : out std_logic;
|
||||
tdin : out std_logic;
|
||||
tcclk : out std_logic
|
||||
-- OHO_DY1 connected to test connector
|
||||
tmosi : out std_logic;
|
||||
tdin : out std_logic;
|
||||
tcclk : out std_logic
|
||||
);
|
||||
end AtomBusMon;
|
||||
|
||||
architecture behavioral of AtomBusMon is
|
||||
|
||||
signal clock_avr : std_logic;
|
||||
signal nrst_avr : std_logic;
|
||||
signal lcd_rw_int : std_logic;
|
||||
signal lcd_db_in : std_logic_vector(7 downto 4);
|
||||
signal lcd_db_out : std_logic_vector(7 downto 4);
|
||||
signal dy_counter : std_logic_vector(31 downto 0);
|
||||
signal dy_data : y2d_type ;
|
||||
signal clock_avr : std_logic;
|
||||
signal nrst_avr : std_logic;
|
||||
signal lcd_rw_int : std_logic;
|
||||
signal lcd_db_in : std_logic_vector(7 downto 4);
|
||||
signal lcd_db_out : std_logic_vector(7 downto 4);
|
||||
signal dy_counter : std_logic_vector(31 downto 0);
|
||||
signal dy_data : y2d_type ;
|
||||
|
||||
signal mux : std_logic_vector(7 downto 0);
|
||||
signal muxsel : std_logic_vector(2 downto 0);
|
||||
signal cmd_edge : std_logic;
|
||||
signal cmd_edge1 : std_logic;
|
||||
signal cmd_edge2 : std_logic;
|
||||
signal cmd : std_logic_vector(3 downto 0);
|
||||
signal mux : std_logic_vector(7 downto 0);
|
||||
signal muxsel : std_logic_vector(2 downto 0);
|
||||
signal cmd_edge : std_logic;
|
||||
signal cmd_edge1 : std_logic;
|
||||
signal cmd_edge2 : std_logic;
|
||||
signal cmd : std_logic_vector(3 downto 0);
|
||||
|
||||
signal addr_sync : std_logic_vector(15 downto 0);
|
||||
signal addr_inst : std_logic_vector(15 downto 0);
|
||||
signal addr_sync : std_logic_vector(15 downto 0);
|
||||
signal addr_inst : std_logic_vector(15 downto 0);
|
||||
|
||||
signal single : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal step : std_logic;
|
||||
signal single : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal step : std_logic;
|
||||
|
||||
signal bw_status : std_logic_vector(19 downto 0);
|
||||
signal bw_status : std_logic_vector(fifo_width - 16 - 1 downto 0);
|
||||
signal bw_status1 : std_logic_vector(fifo_width - 16 - 1 downto 0);
|
||||
|
||||
signal brkpt_reg : std_logic_vector(87 downto 0);
|
||||
signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
|
||||
signal brkpt_enable : std_logic;
|
||||
signal brkpt_active : std_logic;
|
||||
signal brkpt_active1 : std_logic;
|
||||
|
||||
signal watch_active : std_logic;
|
||||
signal watch_din : std_logic_vector(35 downto 0);
|
||||
signal watch_dout : std_logic_vector(35 downto 0);
|
||||
signal watch_empty : std_logic;
|
||||
signal watch_rd : std_logic;
|
||||
signal watch_wr : std_logic;
|
||||
signal brkpt_active1 : std_logic;
|
||||
signal watch_active : std_logic;
|
||||
|
||||
signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
|
||||
signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
|
||||
signal fifo_empty : std_logic;
|
||||
signal fifo_rd : std_logic;
|
||||
signal fifo_wr : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
@ -170,7 +177,7 @@ begin
|
||||
portdin(4) => '0',
|
||||
portdin(5) => '0',
|
||||
portdin(6) => sw1,
|
||||
portdin(7) => not watch_empty,
|
||||
portdin(7) => not fifo_empty,
|
||||
portdout => open,
|
||||
|
||||
-- Mux Port
|
||||
@ -187,17 +194,17 @@ begin
|
||||
|
||||
WatchEvents_inst : entity work.WatchEvents port map(
|
||||
clk => Phi2,
|
||||
din => watch_din,
|
||||
wr_en => watch_wr,
|
||||
rd_en => watch_rd,
|
||||
dout => watch_dout,
|
||||
din => fifo_din,
|
||||
wr_en => fifo_wr,
|
||||
rd_en => fifo_rd,
|
||||
dout => fifo_dout,
|
||||
full => open,
|
||||
empty => watch_empty
|
||||
empty => fifo_empty
|
||||
);
|
||||
|
||||
watch_din <= bw_status & Addr when Sync = '1' else
|
||||
bw_status & addr_inst;
|
||||
|
||||
|
||||
fifo_din <= bw_status1 & addr_inst;
|
||||
|
||||
lcd_rw <= lcd_rw_int;
|
||||
lcd_db <= lcd_db_out when lcd_rw_int = '0' else (others => 'Z');
|
||||
lcd_db_in <= lcd_db;
|
||||
@ -213,68 +220,69 @@ begin
|
||||
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
|
||||
dy_data(2) <= hex & "0000" & "00" & (not nsw2) & sw1;
|
||||
|
||||
mux <= addr_inst(7 downto 0) when muxsel = 0 else
|
||||
addr_inst(15 downto 8) when muxsel = 1 else
|
||||
watch_dout(7 downto 0) when muxsel = 2 else
|
||||
watch_dout(15 downto 8) when muxsel = 3 else
|
||||
watch_dout(23 downto 16) when muxsel = 4 else
|
||||
watch_dout(31 downto 24) when muxsel = 5 else
|
||||
"0000" & watch_dout(35 downto 32) when muxsel = 6 else
|
||||
mux <= addr_inst(7 downto 0) when muxsel = 0 else
|
||||
addr_inst(15 downto 8) when muxsel = 1 else
|
||||
fifo_dout(7 downto 0) when muxsel = 2 else
|
||||
fifo_dout(15 downto 8) when muxsel = 3 else
|
||||
fifo_dout(23 downto 16) when muxsel = 4 else
|
||||
fifo_dout(31 downto 24) when muxsel = 5 else
|
||||
"0000" & fifo_dout(35 downto 32) when muxsel = 6 else
|
||||
"10101010";
|
||||
|
||||
|
||||
-- Combinatorial set of comparators to decode breakpoint/watch addresses
|
||||
brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync)
|
||||
variable bactive : std_logic;
|
||||
variable wactive : std_logic;
|
||||
variable status : std_logic_vector(19 downto 0);
|
||||
variable i : integer;
|
||||
variable reg_addr : std_logic_vector(15 downto 0);
|
||||
variable reg_mode_bi : std_logic;
|
||||
variable i : integer;
|
||||
variable reg_addr : std_logic_vector(15 downto 0);
|
||||
variable reg_mode_bi : std_logic;
|
||||
variable reg_mode_bar : std_logic;
|
||||
variable reg_mode_baw : std_logic;
|
||||
variable reg_mode_wi : std_logic;
|
||||
variable reg_mode_wi : std_logic;
|
||||
variable reg_mode_war : std_logic;
|
||||
variable reg_mode_waw : std_logic;
|
||||
variable bactive : std_logic;
|
||||
variable wactive : std_logic;
|
||||
variable status : std_logic_vector(19 downto 0);
|
||||
begin
|
||||
bactive := '0';
|
||||
wactive := '0';
|
||||
status := "00001010101010101010";
|
||||
status := "00001010101010101010";
|
||||
if (brkpt_enable = '1') then
|
||||
for i in 0 to 3 loop
|
||||
reg_addr := brkpt_reg(i * 22 + 15 downto i * 22);
|
||||
reg_mode_bi := brkpt_reg(i * 22 + 16);
|
||||
reg_mode_bar := brkpt_reg(i * 22 + 17);
|
||||
reg_mode_baw := brkpt_reg(i * 22 + 18);
|
||||
reg_mode_wi := brkpt_reg(i * 22 + 19);
|
||||
reg_mode_war := brkpt_reg(i * 22 + 20);
|
||||
reg_mode_waw := brkpt_reg(i * 22 + 21);
|
||||
for i in 0 to num_comparators - 1 loop
|
||||
reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
|
||||
reg_mode_bi := brkpt_reg(i * reg_width + 16);
|
||||
reg_mode_bar := brkpt_reg(i * reg_width + 17);
|
||||
reg_mode_baw := brkpt_reg(i * reg_width + 18);
|
||||
reg_mode_wi := brkpt_reg(i * reg_width + 19);
|
||||
reg_mode_war := brkpt_reg(i * reg_width + 20);
|
||||
reg_mode_waw := brkpt_reg(i * reg_width + 21);
|
||||
if (Addr = reg_addr) then
|
||||
if (Sync = '1') then
|
||||
if (reg_mode_bi = '1') then
|
||||
bactive := '1';
|
||||
status := "0001" & reg_addr;
|
||||
status := "0001" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_wi = '1') then
|
||||
wactive := '1';
|
||||
status := "1001" & reg_addr;
|
||||
status := "1001" & reg_addr;
|
||||
end if;
|
||||
else
|
||||
if (RNW = '1') then
|
||||
if (reg_mode_bar = '1') then
|
||||
bactive := '1';
|
||||
status := "0010" & reg_addr;
|
||||
status := "0010" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_war = '1') then
|
||||
wactive := '1';
|
||||
status := "1010" & reg_addr;
|
||||
status := "1010" & reg_addr;
|
||||
end if;
|
||||
else
|
||||
if (reg_mode_baw = '1') then
|
||||
bactive := '1';
|
||||
status := "0100" & reg_addr;
|
||||
status := "0100" & reg_addr;
|
||||
end if;
|
||||
if (reg_mode_waw = '1') then
|
||||
wactive := '1';
|
||||
status := "1100" & reg_addr;
|
||||
status := "1100" & reg_addr;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
@ -283,27 +291,26 @@ begin
|
||||
end if;
|
||||
watch_active <= wactive;
|
||||
brkpt_active <= bactive;
|
||||
bw_status <= status;
|
||||
bw_status <= status;
|
||||
end process;
|
||||
|
||||
watch_wr <= '1' when watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') else '0';
|
||||
|
||||
-- 6502 Control
|
||||
-- 6502 Control Commands
|
||||
-- 000x Enable/Disable single strpping
|
||||
-- 001x Enable/Disable breakpoints / watches
|
||||
-- 010x Load register
|
||||
-- 011x Reset
|
||||
-- 1000 Single Step
|
||||
-- 1001 Watch Read
|
||||
syncProcess: process (Phi2)
|
||||
begin
|
||||
if rising_edge(Phi2) then
|
||||
|
||||
-- Command processing
|
||||
cmd_edge1 <= cmd_edge;
|
||||
cmd_edge2 <= cmd_edge1;
|
||||
watch_rd <= '0';
|
||||
fifo_rd <= '0';
|
||||
fifo_wr <= '0';
|
||||
if (cmd_edge2 = '0' and cmd_edge1 = '1') then
|
||||
-- 000x Enable/Disable single strpping
|
||||
-- 001x Enable/Disable breakpoints / watches
|
||||
-- 010x Load register
|
||||
-- 011x Reset
|
||||
-- 1000 Single Step
|
||||
-- 1001 Watch Read
|
||||
|
||||
if (cmd(3 downto 1) = "000") then
|
||||
single <= cmd(0);
|
||||
end if;
|
||||
@ -321,32 +328,34 @@ begin
|
||||
end if;
|
||||
|
||||
if (cmd(3 downto 0) = "1001") then
|
||||
watch_rd <= '1';
|
||||
end if;
|
||||
|
||||
fifo_rd <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Single Stepping
|
||||
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "1000")) then
|
||||
Rdy <= (not brkpt_active);
|
||||
else
|
||||
Rdy <= (not Sync);
|
||||
end if;
|
||||
|
||||
-- 6502 Reset needs to be open collector
|
||||
if (reset = '1') then
|
||||
nRST <= '0';
|
||||
else
|
||||
nRST <= 'Z';
|
||||
end if;
|
||||
|
||||
-- Address monitoring
|
||||
addr_sync <= Addr;
|
||||
-- Latch instruction address for the whole cycle
|
||||
if (Sync = '1') then
|
||||
addr_inst <= Addr;
|
||||
end if;
|
||||
|
||||
-- Breakpoints and Watches written to the FIFO
|
||||
brkpt_active1 <= brkpt_active;
|
||||
|
||||
|
||||
-- Single Stepping
|
||||
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "1000")) then
|
||||
Rdy <= (not brkpt_active);
|
||||
else
|
||||
Rdy <= (not Sync);
|
||||
bw_status1 <= bw_status;
|
||||
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
|
||||
fifo_wr <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user