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Z80: Fix timing of T80 Int Ack cycles

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Change-Id: Id03770dc349f4a6bceea5875dba3f6c55315b311
This commit is contained in:
David Banks 2019-11-08 10:39:12 +00:00
parent c8f997863e
commit 06270af767
2 changed files with 34 additions and 12 deletions
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31
src/T80/T80a.vhd
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@ -125,6 +125,8 @@ architecture rtl of T80a is
signal MCycle : std_logic_vector(2 downto 0); signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0);
signal HALT_n_int : std_logic; signal HALT_n_int : std_logic;
signal iack1 : std_logic;
signal iack2 : std_logic;
begin begin
@ -145,7 +147,7 @@ begin
--A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); --A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
MREQ_n <= MREQ_n_i; MREQ_n <= MREQ_n_i;
IORQ_n <= IORQ_n_i or IReq_Inhibit; -- 0247a IORQ_n <= IORQ_n_i or IReq_Inhibit or Req_inhibit; --DMB
RD_n <= RD_n_i; RD_n <= RD_n_i;
WR_n <= WR_n_j; -- 0247a WR_n <= WR_n_j; -- 0247a
RFSH_n <= RFSH_n_i; RFSH_n <= RFSH_n_i;
@ -275,13 +277,32 @@ begin
RD <= '0'; RD <= '0';
IORQ_n_i <= '1'; IORQ_n_i <= '1';
MREQ <= '0'; MREQ <= '0';
iack1 <= '0';
iack2 <= '0';
elsif CLK_n'event and CLK_n = '0' then elsif CLK_n'event and CLK_n = '0' then
if CEN = '1' then if CEN = '1' then
if MCycle = "001" then if MCycle = "001" then
if TState = "001" then if IntCycle_n = '1' then
RD <= IntCycle_n; -- Normal M1 Cycle
MREQ <= IntCycle_n; if TState = "001" then
IORQ_n_i <= IntCycle_n; RD <= '1';
MREQ <= '1';
IORQ_n_i <= '1';
end if;
else
-- Interupt Ack Cycle
-- 5 T-states: T1 T1 (auto wait) T1 (auto wait) T2 T3
-- Assert IORQ in middle of third T1
if TState = "001" then
iack1 <= '1';
iack2 <= iack1;
else
iack1 <= '0';
iack2 <= '0';
end if;
if iack2 = '1' then
IORQ_n_i <= '0';
end if;
end if; end if;
if TState = "011" then if TState = "011" then
RD <= '0'; RD <= '0';

15
src/Z80CpuMonALS.vhd
View File

@ -102,6 +102,7 @@ architecture behavioral of Z80CpuMonALS is
signal led_trig0 : std_logic; signal led_trig0 : std_logic;
signal led_trig1 : std_logic; signal led_trig1 : std_logic;
signal TState : std_logic_vector(2 downto 0);
begin begin
sw_reset_cpu <= not sw1; sw_reset_cpu <= not sw1;
@ -183,9 +184,9 @@ begin
-- Debugging signals -- Debugging signals
test1 => open, test1 => open,
test2 => open, test2 => TState(0),
test3 => open, test3 => TState(1),
test4 => open test4 => TSTate(2)
); );
-- Test outputs -- Test outputs
@ -195,9 +196,9 @@ begin
test(3) <= MREQ_n_int; test(3) <= MREQ_n_int;
test(4) <= IORQ_n_int; test(4) <= IORQ_n_int;
test(5) <= WAIT_n; test(5) <= WAIT_n;
test(6) <= RESET_n; test(6) <= CLK_n;
test(7) <= CLK_n; test(7) <= TState(2);
test(8) <= RFSH_n_int; test(8) <= TState(1);
test(9) <= INT_n; test(9) <= TState(0);
end behavioral; end behavioral;