Initial checkin of ICE-6809; version now 0.49
Change-Id: I502840a0be0fa58adfc9ddb27c4e2a35a7c2849c
This commit is contained in:
David Banks
parent
10be34c618
commit
20269623ea
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@ -7,6 +7,7 @@ src/AtomBusMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/Z80CpuMon_bd.bmm
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src/MC6809ECpuMon_bd.bmm
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*~
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#*
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firmware/*.o
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:20C00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40
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:20C02000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20
|
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:20C04000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00
|
||||
:20C06000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0
|
||||
:20C08000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0
|
||||
:20C0A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0
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||||
:20C0C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80
|
||||
:20C0E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60
|
||||
:20C10000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F
|
||||
:20C12000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F
|
||||
:20C14000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
||||
:20C16000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF
|
||||
:20C18000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF
|
||||
:20C1A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9F
|
||||
:20C1C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F
|
||||
:20C1E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F
|
||||
:20C20000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E
|
||||
:20C22000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1E
|
||||
:20C24000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
|
||||
:20C26000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDE
|
||||
:20C28000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE
|
||||
:20C2A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9E
|
||||
:20C2C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7E
|
||||
:20C2E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5E
|
||||
:20C30000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D
|
||||
:20C32000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1D
|
||||
:20C34000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD
|
||||
:20C36000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDD
|
||||
:20C38000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBD
|
||||
:20C3A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9D
|
||||
:20C3C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D
|
||||
:20C3E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5D
|
||||
:20C40000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C
|
||||
:20C42000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1C
|
||||
:20C44000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC
|
||||
:20C46000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDC
|
||||
:20C48000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBC
|
||||
:20C4A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9C
|
||||
:20C4C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C
|
||||
:20C4E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5C
|
||||
:20C50000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
|
||||
:20C52000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
|
||||
:20C54000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB
|
||||
:20C56000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB
|
||||
:20C58000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB
|
||||
:20C5A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B
|
||||
:20C5C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
|
||||
:20C5E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
|
||||
:20C60000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
|
||||
:20C62000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
|
||||
:20C64000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
|
||||
:20C66000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
|
||||
:20C68000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
|
||||
:20C6A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
|
||||
:20C6C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
|
||||
:20C6E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
|
||||
:20C70000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39
|
||||
:20C72000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19
|
||||
:20C74000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
|
||||
:20C76000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
|
||||
:20C78000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
|
||||
:20C7A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99
|
||||
:20C7C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79
|
||||
:20C7E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF59
|
||||
:20C80000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF38
|
||||
:20C82000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF18
|
||||
:20C84000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8
|
||||
:20C86000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD8
|
||||
:20C88000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB8
|
||||
:20C8A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF98
|
||||
:20C8C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF78
|
||||
:20C8E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF58
|
||||
:20C90000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF37
|
||||
:20C92000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF17
|
||||
:20C94000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7
|
||||
:20C96000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD7
|
||||
:20C98000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7
|
||||
:20C9A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97
|
||||
:20C9C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77
|
||||
:20C9E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF57
|
||||
:20CA0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF36
|
||||
:20CA2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF16
|
||||
:20CA4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6
|
||||
:20CA6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD6
|
||||
:20CA8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB6
|
||||
:20CAA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF96
|
||||
:20CAC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF76
|
||||
:20CAE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF56
|
||||
:20CB0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF35
|
||||
:20CB2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF15
|
||||
:20CB4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5
|
||||
:20CB6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD5
|
||||
:20CB8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB5
|
||||
:20CBA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF95
|
||||
:20CBC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF75
|
||||
:20CBE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF55
|
||||
:20CC0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF34
|
||||
:20CC2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF14
|
||||
:20CC4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4
|
||||
:20CC6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD4
|
||||
:20CC8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB4
|
||||
:20CCA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF94
|
||||
:20CCC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF74
|
||||
:20CCE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF54
|
||||
:20CD0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF33
|
||||
:20CD2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF13
|
||||
:20CD4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3
|
||||
:20CD6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD3
|
||||
:20CD8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB3
|
||||
:20CDA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF93
|
||||
:20CDC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF73
|
||||
:20CDE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF53
|
||||
:20CE0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF32
|
||||
:20CE2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF12
|
||||
:20CE4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2
|
||||
:20CE6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD2
|
||||
:20CE8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB2
|
||||
:20CEA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF92
|
||||
:20CEC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF72
|
||||
:20CEE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF52
|
||||
:20CF0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF31
|
||||
:20CF2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF11
|
||||
:20CF4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1
|
||||
:20CF6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD1
|
||||
:20CF8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB1
|
||||
:20CFA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF91
|
||||
:20CFC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF71
|
||||
:20CFE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF51
|
||||
:20D00000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF30
|
||||
:20D02000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF10
|
||||
:20D04000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
|
||||
:20D06000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
|
||||
:20D08000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB0
|
||||
:20D0A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF90
|
||||
:20D0C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF70
|
||||
:20D0E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50
|
||||
:20D10000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F
|
||||
:20D12000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F
|
||||
:20D14000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF
|
||||
:20D16000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCF
|
||||
:20D18000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF
|
||||
:20D1A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F
|
||||
:20D1C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6F
|
||||
:20D1E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4F
|
||||
:20D20000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2E
|
||||
:20D22000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0E
|
||||
:20D24000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE
|
||||
:20D26000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCE
|
||||
:20D28000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAE
|
||||
:20D2A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8E
|
||||
:20D2C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6E
|
||||
:20D2E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4E
|
||||
:20D30000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2D
|
||||
:20D32000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0D
|
||||
:20D34000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED
|
||||
:20D36000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCD
|
||||
:20D38000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAD
|
||||
:20D3A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8D
|
||||
:20D3C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6D
|
||||
:20D3E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4D
|
||||
:20D40000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2C
|
||||
:20D42000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0C
|
||||
:20D44000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEC
|
||||
:20D46000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCC
|
||||
:20D48000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAC
|
||||
:20D4A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8C
|
||||
:20D4C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6C
|
||||
:20D4E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4C
|
||||
:20D50000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2B
|
||||
:20D52000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0B
|
||||
:20D54000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEB
|
||||
:20D56000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB
|
||||
:20D58000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAB
|
||||
:20D5A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8B
|
||||
:20D5C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6B
|
||||
:20D5E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4B
|
||||
:20D60000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A
|
||||
:20D62000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A
|
||||
:20D64000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA
|
||||
:20D66000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA
|
||||
:20D68000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA
|
||||
:20D6A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A
|
||||
:20D6C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A
|
||||
:20D6E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A
|
||||
:20D70000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF29
|
||||
:20D72000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF09
|
||||
:20D74000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9
|
||||
:20D76000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9
|
||||
:20D78000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA9
|
||||
:20D7A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF89
|
||||
:20D7C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF69
|
||||
:20D7E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF49
|
||||
:20D80000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF28
|
||||
:20D82000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF08
|
||||
:20D84000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE8
|
||||
:20D86000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC8
|
||||
:20D88000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA8
|
||||
:20D8A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF88
|
||||
:20D8C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF68
|
||||
:20D8E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF48
|
||||
:20D90000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF27
|
||||
:20D92000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07
|
||||
:20D94000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE7
|
||||
:20D96000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7
|
||||
:20D98000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7
|
||||
:20D9A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF87
|
||||
:20D9C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF67
|
||||
:20D9E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF47
|
||||
:20DA0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF26
|
||||
:20DA2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF06
|
||||
:20DA4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE6
|
||||
:20DA6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC6
|
||||
:20DA8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA6
|
||||
:20DAA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF86
|
||||
:20DAC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF66
|
||||
:20DAE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF46
|
||||
:20DB00008D0327FC39B6A00085012706B6A001847F394F398D243402810D270BB7A0010CEA
|
||||
:20DB2000799679917825100F798D0F860DB7A0018D08860AB7A0013502393402B6A0008512
|
||||
:20DB40000227F935023910CE01EE966E8155260A9E6FA684811226026E848E02186F8330AE
|
||||
:20DB60000126FA8E02176F809F19A60243A702A10226063001630120F19F719F279F233065
|
||||
:20DB800089FF389F211F148EDBCECE0076C612BDDCAECE00A7C604BDDCAE863997F0BDDFD0
|
||||
:20DBA000BA8E00B59F8DCEE6CEC60AEF815A26FB8695B7A0008EDC03BDEBE58EDBC69F6F56
|
||||
:20DBC0008655976E200412BDDFD47EDF223B10405000E6CE0C8426020C83B600007EDCBF9B
|
||||
:20DBE0007EDCBE7EDBCD7EE6CE804FC7525932DD1DDE2A1DDDBDDCCE0000000000000000DF
|
||||
:20DC0000000000003638303920455854454E4445442042415349430D2843292031393832A5
|
||||
:20DC2000204259204D4943524F534F46540D0D0034169E76DC789F6AD76C976D35960F73EA
|
||||
:20DC40008E00F4C601BDDB00810826075A27EF301F20348115260A5A27E48608BDDB142095
|
||||
:20DC6000F681031A012705810D260D4F3401BDEBA56F848E00F33581812025C9817B24C5B3
|
||||
:20DC8000C1FA24C1A7805CBDDB1420B92705BDE9C19F7A6E9F007A7EE0A396732603BDDBDE
|
||||
:20DCA000050F73975310260C6A97567EE91FA680A7C05A26F939399D8227FB7EE5003B81FC
|
||||
:20DCC0003A240A812026020E7C803080D039EEC3EF37EEDC00ADF168F1BDE9D4E905E781E8
|
||||
:20DCE000E99AE924E910F26DF235F23EF3AFF3E1F303F569F33DFA3BE92FE94CE953DC9AB7
|
||||
:20DD0000E772F571F631F60179EC0E79EC057BED157BEDDA7FF34650E55946E558464FD25A
|
||||
:20DD200047CF5245CDA7454C53C549C6444154C15052494ED44FCE494E5055D4454EC44E91
|
||||
:20DD40004558D44449CD524541C45255CE524553544F52C55245545552CE53544FD0504F7E
|
||||
:20DD60004BC5434F4ED44C4953D4434C4541D24E45D7455845C354524FCE54524F46C64425
|
||||
:20DD800045CC4445C64C494EC552454E55CD454449D4544142A854CF5355C2544845CE4EC5
|
||||
:20DDA0004FD4535445D04F46C6ABADAAAFDE414EC44FD2BEBDBC46CE5553494EC75347CE6D
|
||||
:20DDC000494ED44142D35553D2524EC45349CE504545CB4C45CE535452A45641CC4153C3DF
|
||||
:20DDE000434852A44154CE434FD35441CE4558D04649D84C4FC7504FD35351D2484558A4D0
|
||||
:20DE00004C454654A45249474854A44D4944A4494E4B4559A44D45CD5641525054D2494E1A
|
||||
:20DE20005354D2535452494E47A4DFE8E133E190E190E190E1C1E18DEB6AE1EFE29CE0BA73
|
||||
:20DE4000E381E5D2E2D6E128E09CE16DE0BEE9DBE0E3E9E2E0F4DFB8DC8CF564F565F7E0CF
|
||||
:20DE6000F724FECEF86AF3F04E46534E52474F4446434F564F4D554C425344442F304944A1
|
||||
:20DE8000544D4F534C535354434E4644414F444E494F464D4E4F4945445355464E4520453C
|
||||
:20DEA00052524F520020494E20000D4F4B0D000D425245414B003064C6129F0FA6848080DC
|
||||
:20DEC0002615AE019F119E3B27099C1127099E0F3A20E59E119F3B9E0F4D398D17DE413324
|
||||
:20DEE000419E433001A68236029C4726F8DF45394F58D31FC3003A250810DF171093172569
|
||||
:20DF0000EEC60CBDDFD4BDEBA9BDEBF88EDE683A8D318D2F8EDE9DBDEBE596684C2703BD91
|
||||
:20DF2000F00EBDEBA98EDEAABDEBE5BDDC3ECEFFFFDF6825F69F839D7C27F0250BBDEA972A
|
||||
:20DF40007EE071A6807EEBFABDE2149E2B9FF1BDEA97D7038D4C2512DC47A384D31BDD1B05
|
||||
:20DF6000EE843702A7809C1B26F896F3271CDC1BDD43DB038900DD41BDDEDBCE00EF370226
|
||||
:20DF8000A7809C4526F89E419F1B8D368D02209B9E19EC8427213304A6C026FCEF84AE84E2
|
||||
:20DFA00020F0DC2B9E19EE84270910A3022306AE8420F31A019F473926FB9E196F806F80DE
|
||||
:20DFC0009F1B9E19BDE1689E279F23BDE09C9E1B9F1D9F1F8E00C99F0BAEE410DE216FE2E4
|
||||
:20DFE0000F2D0F2E0F086E8486809708BDE236BDDEB6326226049E0F3285C609BDDEF0BD9B
|
||||
:20E00000E195DC683416C6A0BDE4F8BDE3CCBDE3CAD654CA7FD450D750108EE0207EE473F6
|
||||
:20E020008EED0EBDEE5D9D8281A426059D7CBDE3CABDEEB6BDE46FDC3B3406868034021C43
|
||||
:20E04000AF8D609E839F2FA6802707813A27227EE500A68197002772EC80DD689F83968C2E
|
||||
:20E06000270F865BBDDB149668BDF015865DBDDB149D7C8D0220C827294D102A01B881FFEE
|
||||
:20E08000270F819E22C9BEDBF1481F893A9D7C6E949D7C8197102714F07EE5009E19301F9C
|
||||
:20E0A0009F3339BDDB05270A8103271281132703977339BDDB0527FB20EE9D8220021A01A0
|
||||
:20E0C00026319E839F2F060032629E688CFFFF27069F299E2F9F2D8EDEAE0D00102AFE42A1
|
||||
:20E0E0007EDF17260EC6209E2D1027FE169F839E299F6839272CBDE66A34069E279D8227AE
|
||||
:20E100000CBDE4F6BDE9C1301F9C7122181F10A3E125121F0383003A250B931B2507DF218C
|
||||
:20E120009F277EDFC77EDF019D821027FE94BDDFC720191F899D7CC1A02716C1A12645C621
|
||||
:20E1400003BDDEF0DE839E6886A134528D037EE03F9D82BDE2148D403001DC2B10936822EC
|
||||
:20E16000029E19BDDFA62517301F9F833926FD86FF973BBDDEB61F148121270BC6048CC6D0
|
||||
:20E180000E7EDF037EE50035529F68DF838D068C8D069F8339C63A865FD7015F9E831F98BD
|
||||
:20E1A000D6019701A68427EC3404A1E027E63001812227EA4C26023001818626E70C04201F
|
||||
:20E1C000E3BDE3CA9D8281812705C6A2BDE4F8964F26130F048DB64D27BA9D7C818426F5C9
|
||||
:20E1E0000A042AF19D7C9D821025FF657EE077BDE98FC681BDE4F8340281A1270481A02671
|
||||
:20E20000830A53260535047EE1359D7C8D06812C27EF35849E749F2B246180309701DC2B4E
|
||||
:20E22000811822DB58495849D32B5849DB018900DD2B9D7C20E2BDE5DB9F3BC6AEBDE4F87B
|
||||
:20E2400096063402BDE3DF350246BDE3D110270C2B9E52DC2110A30224119C1B250DE684E7
|
||||
:20E26000BDE7919E4DBDE8C78E00569F4DBDE8F9DE4D9E3B3726A78410AF02393F52454404
|
||||
:20E280004F0D007EDF03960927079E319F687EE5008EE27BBDEBE59E2F9F8339C6169E683A
|
||||
:20E2A000300127DF8D01398122260BBDE4CDC63BBDE4F8BDEBE88E00F36F848D06C62CE714
|
||||
:20E2C000842016BDEBF8BDEBF5BDDC3E240532647EE0C6C62E399E33864F97099F35BDE5A4
|
||||
:20E2E000DB9F3B9E839F2B9E35A684260996092651BDEBF88DCD9F839D7CD60627239E83C0
|
||||
:20E3000097018122270E301F4F9701BDDC30863A9701862C9702BDE7A2BDE4D2BDE2512022
|
||||
:20E3200006BDEF5BBDEE7C9D822706812C1026FF529E839F359E2B9F839D822721BDE4F64B
|
||||
:20E34000209C9F83BDE19530014D260AC606EE812741EC81DD31A684818626E620989E3518
|
||||
:20E36000D6091026FD3AA68427068EE3707EEBE5393F45585452412049474E4F5245440D9A
|
||||
:20E380000026049E742003BDE5DB9F3BBDDEB62704C60020471F143003BDEE5DA6689754B7
|
||||
:20E3A0009E3BBDEC0BBDEE7C3069BDEEDFE068270CAE6E9F68AEE8109F837EE03F32E81257
|
||||
:20E3C0009D82812C26F49D7C8DBD8D131CFE7D1A010D0625032A998C2B96C6187EDF038D8C
|
||||
:20E3E0006E4F8C34043402C601BDDEF0BDE4AC0F3F9D8280AD25138103240F810149983F9C
|
||||
:20E40000913F2564973F9D7C20E9D63F26331024006B8B07246799061027047789FF340272
|
||||
:20E4200048ABE08EDD0830863502A18424558D9C34028D299E3D3502261D4D1027006A2093
|
||||
:20E440004B0806598D098EE454D73F0F0620D99E837EE16864E578A184243120D3EC013453
|
||||
:20E46000068D08D63F16FF7B7EE500D654A68435203404D64F9E50DE5234546EA49E74A683
|
||||
:20E48000E0272681642703BDE3CC9F3D3504815A2719817D271554D70A3552975C9F5DDFE0
|
||||
:20E4A0005F3504D761D854D762D64F39BDF6F90F069D7C24037EEF5BBDE6262450812E27ED
|
||||
:20E4C000F481A7274081A627E38122260A9E83BDE79C9E649F833981A3260D865ABDE3E33D
|
||||
:20E4E000BDE67143537EE7784C272E8D06BDE3DFC6298CC6288CC62CE19F008326020E7C46
|
||||
:20E50000C6027EDF03867DBDE3E37EF132BDE5DB9F52960626957EEE5D9D7C1F89589D7CEC
|
||||
:20E52000C13823037EE5003404C12A251EC130241C8DC0A6E4BDE3DF8DBCBDE3CF3502DE9F
|
||||
:20E54000523442BDE98F350234068E8D9E3504BEDBF63AAD947EE3CC864F9703BDE671DDC4
|
||||
:20E5600001BDEE93BDE6710D0326069401D40220049A01DA027EE778BDE3D1261096618A01
|
||||
:20E580007F945D975D8E005CBDEEDF20360F060A3FBDE8DBD7569F589E5FBDE8DD965634AC
|
||||
:20E5A00004A0E0270786012403D656409754DE585C5A2604D654200BA680A1C027F3C6FFD3
|
||||
:20E5C000240150CB0159D40A2702C6FF7EEEC5BDE4F6C6018D089D8226F5395F9D82D705E4
|
||||
:20E5E00097379D828D401025FF165FD7069D7C25048D33250A1F899D7C25FC8D2924F88175
|
||||
:20E600002426060306CB809D7CD7389A088028102700750F089E1BDC379C1D271210A3812F
|
||||
:20E62000273E300520F381412504805B80A5398E0074EEE41183E5102728DC1FDD43C3007F
|
||||
:20E6400007DD419E1D9F47BDDEDB9E419F1F9E459F1D9E47DC37ED814F5FED84ED02A70423
|
||||
:20E660009F393990800000009D7CBDE3CA96542B5DBDE3CC964F819025088EE663BDEEDF94
|
||||
:20E68000264CBDEF11DC5239DC053406125F9E3734148DD435349F37DE5234605C9D8281DB
|
||||
:20E6A0002C27EBD703BDE4F03506DD059E1D9C1F2721DC3710A3842706EC02308B20EFC6E1
|
||||
:20E6C000129605260BD603E1042759C6108CC6087EDF03CC0005DD64DC37ED84D603E70434
|
||||
:20E6E000BDDEF09F41C60B4F0D0527053506C30001ED058D5DDD6430020A0326E89F0FD367
|
||||
:20E700000F1025F7FC1F01BDDEF4830035DD1F4F301FA7059C0F26F89E41961F9341ED02F5
|
||||
:20E720009605262DE604D7034F5FDD643506DD5210A305243ADE6427048D17D35230020A46
|
||||
:20E740000326E7EDE358495849E3E1308B30059F393986109745EC05DD174F5F5849250FF8
|
||||
:20E76000086509642404D31725050A4526EE397EE6CB1F40931F214F0F06DD50C6907EEE33
|
||||
:20E78000CBBDE3CCCE01F0BDF02532628E01EF200B9F4D8D5C9F58D75639301F86229701B3
|
||||
:20E7A000970230019F629F58C6FF5CA680270C91012704910226F381222702301F9F64D7BF
|
||||
:20E7C00056DE62118301F022078DC69E62BDE8C99E0B8C00F12605C61E7EDF039656A7000C
|
||||
:20E7E000DC58ED0286FF97069F0D9F5230059F0B390F074F3406DC23A3E0109321250ADD2E
|
||||
:20E80000239E2330019F253584C61A030727CA8D04350420DE9E279F234F5FDD4B9E219F08
|
||||
:20E82000478E00C99C0B27048D3220F89E1B9C1D27048D2220F89F419E419C1F2735EC0269
|
||||
:20E84000D341DD41A6012AF0E60458CB053A9C4127E88D0820F8A60130022A14E684271028
|
||||
:20E86000EC02109323220910934723049F4BDD473005399E4B27FB4FE6845AD347DD439E36
|
||||
:20E88000239F41BDDEDD9E4BDC45ED029E45301F7EE817DC523406BDE4ACBDE3CF35109F4D
|
||||
:20E8A00062E6849E52EB842405C61C7EDF03BDE7919E62E6848D109E4D8D228D0C9E628DC6
|
||||
:20E8C0001CBDE7D07EE3F1AE02DE255C2004A680A7C05A26F9DF2539BDE3CF9E52E6848D8A
|
||||
:20E8E000182613AE07301F9C2326083404D323DD233504300139AE02399C0D26079F0B306C
|
||||
:20E900001B9F0D4F398D037EE7778DCC0F065D39BDE992C601BDE7F19653BDE795A7843225
|
||||
:20E92000627EE7D08D0220DF8DE0275EE684398D484FE1842303E6844F3406BDE7939E4D59
|
||||
:20E940008D9B35043A3504BDE8C920D58D2BA0844020DFC6FFD7539D8281292705BDE4F6EA
|
||||
:20E960008D2D8D1527245F4AA18424CD1F89E08450D15323C4D65320C0BDE4F0EEE4AE654B
|
||||
:20E980009F4DA664E66432671F357EE6CE9D7CBDE3CABDE66D4D26F20E82BDE90A102702A7
|
||||
:20E9A000E1DE839F833AA68434526F849D82BDEF5B3552A784DF83398D079F2BBDE4F6208E
|
||||
:20E9C000CEBDE3CA96542BC2964F819022BCBDEF119E52398DEEE6847EE7778DDB9E2BE795
|
||||
:20E9E00084393401BDE214BDDFA29F66350127129D82271381A726099D7C2706BDE21427F0
|
||||
:20EA00000639CEFFFFDF2B32629E66BDEBA9BDDC97EC8426037EDF229F66EC0210932B22CD
|
||||
:20EA2000F4BDF015BDEBF59E668D10AE9F0066CE00F4A6C027D5BDEBFA20F73004108E0080
|
||||
:20EA4000F4A68027512B15813A260DE684C18427F0C18327EC8C86218D3020E5CEDBE481D6
|
||||
:20EA6000FF2604A6803345847F334A6DC427E7A0C42AF6ABC4EE414A2B066DC02AFC20F709
|
||||
:20EA8000A6C48D066DC02AF820B7108C01ED2406847FA7A06FA4399E83CE00F30F430F4482
|
||||
:20EAA000A68027210D43270FBDE626241881302504813923100F438120270A9742812227CF
|
||||
:20EAC000380D442719A7C02706813A27CF20D16FC06FC01F308300F18E00F29F8339813F7B
|
||||
:20EAE0002604868720DF81272613CC3A83EDC10F42A68027D0914227CCA7C020F481302543
|
||||
:20EB000004813C25C0301F34500F41CEDBE40F42334AA6C4273110AE41AEE4E6A0E0802771
|
||||
:20EB2000FAC180263832623540DA4296412606C1842606863AEDC12094E7C0C18626020C5F
|
||||
:20EB400044C18227AA2086CEDBE9034126C03550A680A7C0BDE62625EC034320E80C424A29
|
||||
:20EB600027AE313FE6A02AFC20AF27398D0139BDFACF273E819F2753812C2737813B2760DB
|
||||
:20EB8000BDE3DF960634022606BDF022BDE79A8D573504BDDC305D26089D82812C27148DE6
|
||||
:20EBA000549D8226CF860D2051BDDC3027F7966C26F339BDDC30270AD66CD16B25068DE599
|
||||
:20EBC000201ED66CD06A24FC502010BDE98D81291026F92CBDDC30D06C23058D185A26FB56
|
||||
:20EBE0009D7C7EEB72BDE79CBDE8DB5C5A27C3A6808D0720F786208C863F7EDB148EF10904
|
||||
:20EC00002009BDED78035403622003BDED785D102702808E005C1F895D276CD04F2769253C
|
||||
:20EC20000A974F966197548E004F50C1F82F594F6401BDED03D6622A0B6301630263036334
|
||||
:20EC40000443890097639653996097539652995F97529651995E97519650995D97505D2A45
|
||||
:20EC60004425028D5D5F9650262E965197509652975196539752966397530F63CB08C12825
|
||||
:20EC80002DE44F974F9754398D6D5F20A85C086309530952095109502AF3964F3404A0E0FE
|
||||
:20ECA000974F23DE8C2508086386009763200C0C4F2728065006510652065324048D0D27AC
|
||||
:20ECC000EE39035403500351035203539E5230019F5226069E5030019F5039C60A7EDF03AF
|
||||
:20ECE0008E0012A6049763A603A704A602A703A601A702965BA701CB082FE89663C008276F
|
||||
:20ED00000C6701660266036604465C26F43981000000008D6327608D7886009713971497E0
|
||||
:20ED2000159716D6538D22D663D78BD6528D1AD663D78AD6518D12D663D789D6508D0CD641
|
||||
:20ED400063D788BDEE547EEC652795439613562726241696169B6097169615995F97159665
|
||||
:20ED600014995E97149613995D46971306140615061606634F20D539EC0197618A80DD5DEE
|
||||
:20ED8000D661D854D762EC03DD5FA684975CD64F394D27169B4F464928108B80974F270CD2
|
||||
:20EDA000966297543996544320023262102AFED27EECDBBDEEA8270D8B0225F40F62BDECBE
|
||||
:20EDC000160C4F27EB398420000000BDEEA88EEDC65FD762BDEE5D8C8D9E2773004F8DB1C1
|
||||
:20EDE0000C4F27CC8E0013C604D703C6019650915D26139651915E260D9652915F26079608
|
||||
:20EE00005391602601431FA859240AE7800A032B34272EC6011F8A250E0860095F095E09EB
|
||||
:20EE20005D25E32BC820DF966090539760965F9252975F965E9251975E965D9250975D2027
|
||||
:20EE4000D8C64020D0565656D7638D087EEC65C6147EDF039E139F509E159F52393402EC6B
|
||||
:20EE60000197548A80DD500F63E684AE039F52D74F35828E004520068E00408C9E3B964F03
|
||||
:20EE8000A78496548A7F9450A7019651A702DE52EF0339966197549E5C9F4F0F63965E9716
|
||||
:20EEA0005196549E5F9F5239DC4FDD5C9E519F5E9E539F604D39D64F2708D65459C6FF2569
|
||||
:20EEC0000150398DF1D7500F51C68896508080D74FDC74DD52976397547EEC610F5439E698
|
||||
:20EEE0008427D3E601D8542BD1D64FE184261DE601CA7FD450E1012613D651E102260DD636
|
||||
:20EF000052E1032607D653E00426013956D85420ABD64F273DC0A096542A05035BBDECC407
|
||||
:20EF20008E004FC1F82E06BDECF70F5B390F5B96544906507EED03D64FC1A0241D8DD2D766
|
||||
:20EF4000639654D754808086A0974F965397017EEC61D750D751D752D753399E749F549F62
|
||||
:20EF60004F9F519F529F479F452564BDF698812D260403552004812B26049D7C2551812E5B
|
||||
:20EF80002728814526289D7C256481A7270E812D270A81A62708812B2704200603489D7C79
|
||||
:20EFA000254C0D48270800472004034626CC96479045974727122A09BDEDCB0C4726F920B3
|
||||
:20EFC00007BDEDB30A4726F996552A8E7EF132D645D046D7453402BDEDB33504C0308D0281
|
||||
:20EFE0002098BDEE78BDEEC58E00407EEC0BD6475858DB475880303404ABE09747209F9B91
|
||||
:20F000003EBC1FFD9E6E6B27FD9E6E6B28008EDEA48D0CDC68DD50C69043BDEECF8D037E65
|
||||
:20F02000EBE5CE01F18620D6542A02862DA7C0DF6497548630D64F102700C64FC18022086A
|
||||
:20F040008EF009BDED1386F797458EF004BDEEE92E0F8EEFFFBDEEE92E0EBDEDB30A4520A8
|
||||
:20F06000F1BDEDCB0C4520E2BDEBFDBDEF11C60196458B0A2B09810B24054A1F8986024A91
|
||||
:20F080004A9747D7452E0DDE64862EA7C05D27048630A7C08EF10EC6809653AB0397539605
|
||||
:20F0A00052A90297529651A90197519650A98497505C565928E32403C00B50CB2F30041F52
|
||||
:20F0C00098847FA7C00A452604862EA7C053C4808CF13226C4A6C2813027FA812E26023326
|
||||
:20F0E0005F862BD647271C2A03862D50A7428645A741862F4CC00A24FBCB3AED436F4520E1
|
||||
:20F1000004A7C46F418E01F1398000000000FA0A1F0000989680FFF0BDC0000186A0FFFF35
|
||||
:20F12000D8F0000003E8FFFFFF9C0000000AFFFFFFFF964F27020354399F64BDEE788D0527
|
||||
:20F140008D088E00407EED139F64BDEE739E64E680D7559F648DEE9E6430059F64BDEC0BAD
|
||||
:20F160008E00450A5526EE39BDEEB62B1F27158D10BDEE788D0E8E00408DCA8EED0EBDEC77
|
||||
:20F180000B7EEF379EB19F509EB39F52BEF1B99F5DBEF1BB9F5FBDED19DC8AC3658BDDB308
|
||||
:20F1A000DD52DC88C9B08905DDB1DD500F548680974F961597637EEC6540E64DABBDEEA8C6
|
||||
:20F1C0008EF202D661BDEDD2BDEEA88DB40F62965CD64FBDEC058EF207BDEC0296543402DE
|
||||
:20F1E0002A09BDEBFD96542B05030ABDF1328EF207BDEC0B35024D2A03BDF1328EF20C7E5A
|
||||
:20F20000F13983490FDAA27F000000000584E61A2D1B862807FBF88799688901872335DFA5
|
||||
:20F22000E186A55DE72883490FDAA2A154468F138F524389CD8EF268BDEC0B7EF1BDBDEE35
|
||||
:20F24000780F0A8DF68E004ABDEE7E8E0040BDEE5D0F54960A8D0C0D4F1027FA7E8E004A44
|
||||
:20F260007EEDD834027EF1EB81490FDAA2965434022A028D24964F3402818125058EED0E99
|
||||
:20F280008DDE8EF29DBDF1393502818125068EF268BDEC0235024D2A037EF132390B76B349
|
||||
:20F2A00083BDD3791EF4A6F57B83FCB0107C0C1F67CA7CDE53CBC17D1464704C7DB7EA512A
|
||||
:20F2C0007A7D6330887E7E9244993A7E4CCC91C77FAAAAAA138100000000037F5E56CB79FE
|
||||
:20F2E00080139B0B6480763893168238AA3B20803504F334813504F3348080000000803169
|
||||
:20F300007217F8BDEEB6102FF3C48EF2EF964F808034028680974FBDEC0B8EF2F4BDEDD8F5
|
||||
:20F320008EED0EBDEC028EF2DABDF1398EF2F9BDEC0B3504BDEFE28EF2FE7EED13BDEEA815
|
||||
:20F340008EF109BDEE5D27674D26037EEC838E004ABDEE7E5F96612A10BDEF378E004A964A
|
||||
:20F3600061BDEEE9260343D601BDEE953404BDF3038E004ABDED138D363502461025FDB271
|
||||
:20F38000398138AA3B29077134583E5674167EB31B772FEEE3857A1D841C2A7C6359580A08
|
||||
:20F3A0007E75FDE7C6803172181081000000008EF381BDED13BDEE78964F818825037EED81
|
||||
:20F3C000A5BDEF3796018B8127F44A34028E0040BDEC028EF386BDF1480F623502BDED910E
|
||||
:20F3E00039BDEEB62B037EEF3703548DF97EF132BDF81E326286019798BDDFA21025ED7F27
|
||||
:20F40000BDEA3B1F208300F5D797DC2BBDF015BDEBF58E00F4D69826255FBDF544BDFCE94D
|
||||
:20F42000250B80303402860A3DEBE020EDC001C90181412605BDEBA520BB814C260B8D31B5
|
||||
:20F440000F98BDEBA520C33262810D260D8D22BDEBA58E00F49F837EDF4B814527F1815188
|
||||
:20F460002606BDEBA57EDF228D0220AD812026108CC6F9A6842708BDDB1430015A26F43933
|
||||
:20F48000814426486D8427F78D045A26F7390A97311F3121A621A7A426F8398149271381B8
|
||||
:20F4A00058270D8148265C6F841F108300F5D7978DBFBDF544810D278E811B272581082651
|
||||
:20F4C000228C00F427EC8D458DC420E6814326CB6D84270EBDF544250220F5A7808D375AFC
|
||||
:20F4E00026EE39D697C1F9260220C734106D8026FCE682E701ACE426F83262A7808D170CCD
|
||||
:20F500009720AF810826128D045A26FB398C00F427D0301F86087EDB14814B2705805327CC
|
||||
:20F52000013934028D1E3402A68427166D6126068DE430012003BDF48EA684A1E426E95AFD
|
||||
:20F5400026E635A0BDDB00817F24F9815F2602861B810D270E811B270A8108270681202560
|
||||
:20F56000E31A0139864F978C398600D6791D7EE778BDE4F3DC1F3406BDE5DBBDE4F0350642
|
||||
:20F580001E109C1F26517EE7789D7CBDE4F3BDE5DB3410EC02109321230493272312E6848E
|
||||
:20F5A000BDE7F13410AE62BDE8C73550AF423440BDE9BC34045D271FC6FF81292703BDE990
|
||||
:20F5C000BC3404BDE4F0C6AEBDE4F88D2E1F13AE62A684A06124037EE6CE4CA1E42402A77A
|
||||
:20F5E000E4A6611E89AE025A3A4D270DA1E42302A6E41F891E31BDDCAE3596BDE3DF7EE892
|
||||
:20F60000D8BDE4F3BDE98F3404BDE4F6BDE3DFBDE4F096062605BDE9922003BDE928340442
|
||||
:20F62000E661BDE79335062705A7805A26FB7EE91FBDE4F3BDE3DFC601340496062610BD1C
|
||||
:20F64000E992E7E42791BDE4F6BDE3DFBDE3CF9E523410BDE4F6BDF5FB3414BDE4F0AE63C5
|
||||
:20F66000BDE8DD3404E1662523A661271CE6665A3A3184EE62E661A6E4A0664CA161250CBC
|
||||
:20F68000A680A1C0260C5A26F7E666215F32677EE7776C66302120D98126265C32620F52BF
|
||||
:20F6A0000F538E00529D7C814F2712814827239D82200C81381022EE47C6038D2A9D7C25AA
|
||||
:20F6C000F20F500F510F060F630F54C6A0D74F7EEC659D7C250BBDE62625E6814724E280C9
|
||||
:20F6E00007C6048D0220EB680169841025F5EC5A26F58030AB01A7013935400F069E839D39
|
||||
:20F700007C8126279981B0275E81FF26089D7C8183102700AB9F836EC49E68300126D9C653
|
||||
:20F72000167EDF03AE9F00838CFF83102700748D238DE6BDE4F3C680D708BDE5DB8D25BD02
|
||||
:20F74000E4F0C6AEBDE4F89E4BDC83ED84DC39ED027EE18DC6B0BDE4F8C680D7088A80BD24
|
||||
:20F76000E5E09F4B7EE3CC8DEB3410BDE4EB8DF43540C632AE4227A9109E83EEC4DF83A6CC
|
||||
:20F78000043402EC84EE023476BDEE7EBDE3CA3576ED84EF023502A7049D821026ED6110F0
|
||||
:20F7A0009F83399D7C8D0934108D2D3540AFC4395F9D7C240680301F899D7C9E8D583A3917
|
||||
:20F7C0008DEEAE843410BDE4EB8E004F96062707BDE8DB9E52960639C6AEBDE4F87EE9C18B
|
||||
:20F7E0001027EEEABDE214BDDFA29F939D82271081A7263B9D7C27048D24200486FF972B98
|
||||
:20F80000DE938CEEC4ECC42706EC42932B23F49E938D15BDDFC29E93BDDF927EDF22BDE2AB
|
||||
:20F82000147EDCB7A6C0A78011931B26F79F1B39BDF7199D7C8122260BBDE4CDC63BBDE47D
|
||||
:20F84000F8BDEBE8327EBDE2C93262BDE5DB9F3BBDE3CF8E00F34FBDE7A07EE251BDE21436
|
||||
:20F860009E2B399E919F2B7EDFA2BDDFC7CC000ADD95DD8F5FDD919D8224068DE09F959D23
|
||||
:20F8800082271BBDE4F624068DD39F919D82270EBDE4F624068DC69F8F2749BDDCB78DC3AD
|
||||
:20F8A0009F939E958DBF9C93253A8D1CBDF93EBDDF908DAF9F938D3A8D0F8D36BDF9D9BD60
|
||||
:20F8C000DFC7BDDF907EDF22864F97989E93DC958D150D982602ED02AE848D0BD38F25047E
|
||||
:20F8E00081FA25EE7EE6CE3406EC84350626023262399E19301F30018DED30033001A6842F
|
||||
:20F9000027F49F0F4A270C4A272A4A26EF8603A78020E7EC016A0227014FE6036A042701A1
|
||||
:20F920005FED01DD2BBDDFA29E0F25E1DC476C80ED8420C66F84AE01AE029F4720EA9E1922
|
||||
:20F9400020049E8330018D9F300230019F839D7C4D27EF2AF99E8381FF27EF81A22712814D
|
||||
:20F9600084270E818126E79D7C81A0270481A126DB9D7C25049D8220D79E833410BDE214C7
|
||||
:20F980009E83A682BDFCE925F930011F10E061C0052720250A3384503085BDF82820149F16
|
||||
:20F9A000479E1B9F435030859F419F1BBDDEDB9E459F8335108601A784A702A704D62B26D9
|
||||
:20F9C00004C6016C02E701D62C2604C6016C04E7039D82812C279A209C9E19301F3001EC4D
|
||||
:20F9E00002DD68BDF8E730033001A68427EF4A271B800226F334108EFA36BDEBE5AEE4EC4C
|
||||
:20FA000001BDF015BDF00EBDEBA535103410EC01DD52BDF6C1BDF0223540C6053001A68498
|
||||
:20FA200027055AA7C020F530C45D27BE31C433C5BDF82830A420B3554C2000BDE9C48E0163
|
||||
:20FA4000F0C60434045F860408530952594A26F85D260AA6E44A27058C01F0270CCB30C15B
|
||||
:20FA6000392302CB07E7806F8435045A26D532628E01EF7EE79C860197995ABDFC179D825B
|
||||
:20FA800010270093D793BDE3DFBDE3CF9E529F4DD699BDE931BDEBE89E52D699E0845A1065
|
||||
:20FAA0002B014FBDEBF520F6D7939F0F86029799A684812527C4812026070C9930015A2669
|
||||
:20FAC000EF9E0FD6938625BDFC17BDDB14202981B12701393262BDE3E1BDE3CFC63BBDE4F8
|
||||
:20FAE000F89E529F952006969727089E950F97E68426037EE6CEAE020F9A0F99A680812101
|
||||
:20FB00001027FF728123275B5A2616BDFC17BDDB149D8226D296972603BDEBA59E957EE8B2
|
||||
:20FB2000DD812B2609BDFC178608979A20CC812E274E81251027FF70A184268B8124271967
|
||||
:20FB4000812A26F6969A8A20979AC1022511A6018124260B5A30010C99969A8A10979A3002
|
||||
:20FB6000010C990F980C995A2749A680812E271E812327F1812C2621969A8A40979A20E5CF
|
||||
:20FB8000A68481231026FF3F8601979830010C985A2720A680812327F5815E2616A18426AB
|
||||
:20FBA00012A101260EA102260AC1042506C00430040C9A301F0C99969A850826180A995D0D
|
||||
:20FBC0002713A684802D270681FE260986088A049A9A979A5A9D821027FF3CD793BDE3CAF9
|
||||
:20FBE00096999B9881111022EAE4BDFC24301FBDEBE50F979D82270D9797813B2705BDE4A8
|
||||
:20FC0000F620029D7C9E95E684D093AE023AD6931026FEE47EFB113402862B0D9A2703BD49
|
||||
:20FC2000DB143582CE01F2C620969A85082702C62B0D542A040F54C62DE7C0C630E7C084F3
|
||||
:20FC400001102601078EF009BDEEE92B15BDF022A68026FCA682A7018C01F126F78625A736
|
||||
:20FC60008439964F97472703BDFE0C9647102B0081409B998009BDFD29BDFEA2BDFE4196AB
|
||||
:20FC800047BDFEC09647BDFE8896982602335F4ABDFD29BDFDC44D2706C12A2702E7C06F4B
|
||||
:20FCA000C48E01F130019F0F963A901090992738A684812027EE812A27EA4F3402A6808161
|
||||
:20FCC0002D27F8812B27F4910027F08130260EA6018D1625083502A78226FA20C735024D22
|
||||
:20FCE00026FB9E0F8625A7823981302504803A80C639969827014A9B472B014F34022A0AAF
|
||||
:20FD00003402BDEDCB35024C20F49647A0E097478B092B199699800990478D0DBDFEA220E8
|
||||
:20FD20001D34028630A7C035024A2AF53996998DF8BDFE8C86F790478DEF0F450F97BDFEFA
|
||||
:20FD40004196982602DE399B4716FF43964F34022703BDFE0C969827014A9B997F01F1D694
|
||||
:20FD60009AC40426037301F1BB01F1800934022A0A3402BDEDCB35024C20F4A6E42B014FAC
|
||||
:20FD8000409B994CBB01F197450F97BDFE413502BDFEC096982602335FE6E02709D647CB00
|
||||
:20FDA00009D099F001F1862B5D2A03862D50A7418645A7C1862F4CC00A24FBCB3AEDC16F8A
|
||||
:20FDC000C47EFC938E01F2E68434048620D69AC52035042708862AC12026021F893404A78C
|
||||
:20FDE00080E6842710C145270CC13027F2C12C27EEC12E26048630A782969A85102704C6EF
|
||||
:20FE000024E782840435042602E7823934404F9747D64FC18022118EF009BDED13964780EF
|
||||
:20FE20000920ECBDEDCB0C478EF004BDEEE92EF38EEFFFBDEEE92E07BDEDB30A4720F13575
|
||||
:20FE4000C03440BDEBFDBDEF1135408EF10EC6808D369653AB0397539652A902975296511D
|
||||
:20FE6000A90197519650A98497505C565928E32403C00B50CB2F30041F98847FA7C053C438
|
||||
:20FE8000808CF13226CA6FC40A452609DF39862EA7C00F97390A97260886039797862CA7A1
|
||||
:20FEA000C03996478B0A97454C800324FC8B059797969A8440260297973934028DCA350207
|
||||
:20FEC0004A2B0A34028630A7C0A6E026ED3981891027F95C7EE500FFFFFFFFFFFFFFFFFF8E
|
||||
:20FEE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF22
|
||||
:20FF0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01
|
||||
:20FF2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1
|
||||
:20FF4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC1
|
||||
:20FF6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA1
|
||||
:20FF8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81
|
||||
:20FFA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF61
|
||||
:20FFC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF41
|
||||
:20FFE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000009B009E00AA00A700A100A4DB4621
|
||||
:00000001FF
|
||||
|
|
@ -0,0 +1,564 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="src/MC6809ECpuMon.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/MC6809ECpuMon.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerLatch.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/SYS09/cpu09l.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/MC6809ECpuMon.bmm" xil_pn:type="FILE_BMM">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-23T12:17:55" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="614C752717807585A7E3847C608873AC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/MC6809ECpuMon" xil_pn:name="src/MC6809ECpuMon.ucf"/>
|
||||
<binding xil_pn:location="/MC6809EECpuMon" xil_pn:name="src/MC6809ECpuMon.bmm"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -10,12 +10,14 @@
|
|||
* VERSION and NAME are used in the start-up message
|
||||
********************************************************/
|
||||
|
||||
#define VERSION "0.48"
|
||||
#define VERSION "0.49"
|
||||
|
||||
#if (CPU == Z80)
|
||||
#define NAME "ICE-T80"
|
||||
#elif (CPU == 6502)
|
||||
#define NAME "ICE-T65"
|
||||
#elif (CPU == 6809)
|
||||
#define NAME "ICE-6809"
|
||||
#else
|
||||
#error "Unsupported CPU type"
|
||||
#endif
|
||||
|
|
@ -276,7 +278,7 @@ void (*cmdFuncs[NUM_CMDS])(char *params) = {
|
|||
********************************************************/
|
||||
|
||||
// The space available for address comparators depends on the size of the CPU core
|
||||
#if (CPU == Z80)
|
||||
#if ((CPU == Z80) || (CPU == 6809))
|
||||
#define MAXBKPTS 4
|
||||
#else
|
||||
#define MAXBKPTS 8
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
# Paths that will need changing
|
||||
|
||||
ATOMFPGA=$(HOME)/atom/AtomBusMon
|
||||
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
|
||||
XILINX=/opt/Xilinx/14.7
|
||||
|
||||
# Shouldn't need to make changes below this point
|
||||
|
||||
BIT_FILE=$(ATOMFPGA)/working/MC6809ECpuMon.bit
|
||||
BMM_FILE=$(ATOMFPGA)/src/MC6809ECpuMon_bd.bmm
|
||||
|
||||
|
||||
# Papilio dev environment
|
||||
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
|
||||
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
|
||||
SREC_CAT=srec_cat
|
||||
GAWK=gawk
|
||||
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem
|
||||
|
||||
# AVR dev environment
|
||||
MCU=atmega103
|
||||
F_CPU=15855484
|
||||
CC=avr-gcc
|
||||
OBJCOPY=avr-objcopy
|
||||
|
||||
CFLAGS=-DCPU=6809 -DCPUEMBEDDED -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues -mno-interrupts
|
||||
|
||||
OBJECTS=AtomBusMon.o dis6809.o regs6809.o status.o
|
||||
|
||||
build: avr6809cpu.bit
|
||||
|
||||
avr6809cpu.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr6809cpu.bit
|
||||
|
||||
avr_progmem.mem: avr_progmem.hex
|
||||
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
|
||||
$(GAWK) ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
|
||||
rm tmp.mem
|
||||
|
||||
avr_progmem.hex : avr_progmem.out
|
||||
$(OBJCOPY) -R .eeprom -O ihex avr_progmem.out avr_progmem.hex
|
||||
avr_progmem.out : $(OBJECTS)
|
||||
$(CC) $(CFLAGS) -o avr_progmem.out -Wl,-Map,avr_progmem.map $^
|
||||
%.o : %.c
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
%.o : %.S
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
|
||||
.phony: clean
|
||||
|
||||
clean:
|
||||
rm -f avr6809cpu.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
||||
|
|
@ -0,0 +1,487 @@
|
|||
/* dis6809.c -- 6809 disassembler
|
||||
Copyright (C) 1998 Jerome Thoen
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
|
||||
#include "AtomBusMon.h"
|
||||
|
||||
static const int size[] = {
|
||||
2,1,1,2,2,1,2,2,2,2,2,1,2,2,2,2,
|
||||
1,1,1,1,1,1,3,3,1,1,2,1,2,1,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,1,1,1,1,2,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
2,1,1,2,2,1,2,2,2,2,2,1,2,2,2,2,
|
||||
3,1,1,3,3,1,3,3,3,3,3,1,3,3,3,3,
|
||||
2,2,2,3,2,2,2,1,2,2,2,2,3,2,3,1,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
2,2,2,3,2,2,2,1,2,2,2,2,3,1,3,1,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,2,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,4,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,3,3,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,3,3,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,4,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,3,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,3,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,4,4,
|
||||
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,2,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,1,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,1,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 };
|
||||
|
||||
unsigned char get_memb(unsigned int addr) {
|
||||
loadAddr(addr);
|
||||
return readMemByteInc();
|
||||
}
|
||||
|
||||
#ifdef FULLDISASSEMBLER
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
typedef unsigned char tt_u8;
|
||||
typedef signed char tt_s8;
|
||||
typedef unsigned short tt_u16;
|
||||
typedef signed short tt_s16;
|
||||
|
||||
|
||||
unsigned int get_memw(unsigned int addr) {
|
||||
loadAddr(addr);
|
||||
return readMemByteInc() + (readMemByteInc() << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
modes:
|
||||
1 immediate
|
||||
2 direct
|
||||
3 indexed
|
||||
4 extended
|
||||
5 inherent
|
||||
6 relative
|
||||
*/
|
||||
|
||||
static const int mode[] = {
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
0,0,5,5,0,0,6,6,0,5,5,0,5,5,5,5,
|
||||
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
|
||||
3,3,3,3,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,6,1,0,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,1,0,0,0,0,0,0,0,0,1,0,1,0,
|
||||
0,0,0,2,0,0,0,0,0,0,0,0,2,0,2,2,
|
||||
0,0,0,3,0,0,0,0,0,0,0,0,3,0,3,3,
|
||||
0,0,0,4,0,0,0,0,0,0,0,0,4,0,4,4,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,4,
|
||||
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,
|
||||
0,0,0,2,0,0,0,0,0,0,0,0,2,0,0,0,
|
||||
0,0,0,3,0,0,0,0,0,0,0,0,3,0,0,0,
|
||||
0,0,0,4,0,0,0,0,0,0,0,0,4,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
|
||||
|
||||
|
||||
static const char inst[] = "\
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
-- -- NOP SYNC?? ?? LBRALBSR?? DAA ORCC?? ANDCSEX EXG TFR \
|
||||
BRA BRN BHI BLS BCC BLO BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE \
|
||||
LEAXLEAYLEASLEAUPSHSPULSPSHUPULU?? RTS ABX RTI CWAIMUL ?? SWI \
|
||||
NEGA?? ?? COMALSRA?? RORAASRAASLAROLADECA?? INCATSTA?? CLRA\
|
||||
NEGB?? ?? COMBLSRB?? RORBASRBLSLBROLBDECB?? INCBTSTB?? CLRB\
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
SUBACMPASBCASUBDANDABITALDA ?? EORAADCAORA ADDACMPXBSR LDX ?? \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB ?? EORBADCBORB ADDBLDD ?? LDU ?? \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? LBRNLBHILBLSLBCCLBLOLBNELBEQLBVCLBVSLBPLLBMILBGELBLTLBGTLBLE\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? SWI2\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY ?? \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? SWI3\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ";
|
||||
|
||||
static const char regi[] = { 'X', 'Y', 'U', 'S' };
|
||||
|
||||
static const char *exgi[] = { "D", "X", "Y", "U", "S", "PC", "??", "??", "A",
|
||||
"B", "CC", "DP", "??", "??", "??", "??" };
|
||||
|
||||
static const char *pshsregi[] = { "PC", "U", "Y", "X", "DP", "B", "A", "CC" };
|
||||
static const char *pshuregi[] = { "PC", "S", "Y", "X", "DP", "B", "A", "CC" };
|
||||
|
||||
/* disassemble one instruction at adress adr and return its size */
|
||||
|
||||
char hexdigit(tt_u16 v)
|
||||
{
|
||||
v &= 0xf;
|
||||
if (v <= 9)
|
||||
return '0' + v;
|
||||
else
|
||||
return 'A' - 10 + v;
|
||||
}
|
||||
|
||||
char *hex8str(tt_u8 v)
|
||||
{
|
||||
static char tmpbuf[3] = " ";
|
||||
|
||||
tmpbuf[1] = hexdigit(v);
|
||||
tmpbuf[0] = hexdigit(v >> 4);
|
||||
|
||||
return tmpbuf;
|
||||
}
|
||||
|
||||
char *hex16str(tt_u16 v)
|
||||
{
|
||||
static char tmpbuf[5] = " ";
|
||||
|
||||
tmpbuf[3] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[2] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[1] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[0] = hexdigit(v);
|
||||
|
||||
return tmpbuf;
|
||||
}
|
||||
|
||||
static const char ccbits[] = "EFHINZVC";
|
||||
|
||||
char *ccstr(tt_u8 val)
|
||||
{
|
||||
static char tempbuf[9] = " ";
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (val & 0x80)
|
||||
tempbuf[i] = ccbits[i];
|
||||
else
|
||||
tempbuf[i] = '.';
|
||||
val <<= 1;
|
||||
}
|
||||
|
||||
return tempbuf;
|
||||
}
|
||||
|
||||
unsigned int disassemble(unsigned int addr)
|
||||
{
|
||||
int d = get_memb(addr);
|
||||
int s, i;
|
||||
tt_u8 pb;
|
||||
char reg;
|
||||
|
||||
FILE *stream = &ser0stream;
|
||||
|
||||
fprintf(stream, "%04hX: %04hX %04hX ", addr, get_memw(addr), get_memw(addr + 2));
|
||||
|
||||
if (d == 0x10)
|
||||
d = get_memb(addr + 1) + 0x100;
|
||||
|
||||
if (d == 0x11)
|
||||
d = get_memb(addr + 1) + 0x200;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
fputc(inst[d * 4 + i], stream);
|
||||
|
||||
fputs(" ", stream);
|
||||
|
||||
s = size[d];
|
||||
|
||||
switch(mode[d]) {
|
||||
case 1: /* immediate */
|
||||
fputs("#$", stream);
|
||||
if (s == 2)
|
||||
fputs(hex8str(get_memb(addr + 1)), stream);
|
||||
else
|
||||
fputs(hex16str(get_memw(addr + s - 2)), stream);
|
||||
break;
|
||||
case 2: /* direct */
|
||||
fputs("<$", stream);
|
||||
fputs(hex8str(get_memb(addr + s - 1)), stream);
|
||||
break;
|
||||
case 3: /* indexed */
|
||||
pb = get_memb(addr + s - 1);
|
||||
reg = regi[(pb >> 5) & 0x03];
|
||||
|
||||
if (!(pb & 0x80)) { /* n4,R */
|
||||
if (pb & 0x10)
|
||||
fprintf(stream, "-$%s,%c", hex8str(((pb & 0x0f) ^ 0x0f) + 1), reg);
|
||||
else
|
||||
fprintf(stream, "$%s,%c", hex8str(pb & 0x0f), reg);
|
||||
}
|
||||
else {
|
||||
if (pb & 0x10)
|
||||
fputc('[', stream);
|
||||
switch (pb & 0x0f) {
|
||||
case 0: /* ,R+ */
|
||||
fprintf(stream, ",%c+", reg);
|
||||
break;
|
||||
case 1: /* ,R++ */
|
||||
fprintf(stream, ",%c++", reg);
|
||||
break;
|
||||
case 2: /* ,-R */
|
||||
fprintf(stream, ",-%c", reg);
|
||||
break;
|
||||
case 3: /* ,--R */
|
||||
fprintf(stream, ",--%c", reg);
|
||||
break;
|
||||
case 4: /* ,R */
|
||||
fprintf(stream, ",%c", reg);
|
||||
break;
|
||||
case 5: /* B,R */
|
||||
fprintf(stream, "B,%c", reg);
|
||||
break;
|
||||
case 6: /* A,R */
|
||||
fprintf(stream, "A,%c", reg);
|
||||
break;
|
||||
case 8: /* n7,R */
|
||||
s += 1;
|
||||
fprintf(stream, "<$%s,%c", hex8str(get_memb(addr + s - 1)), reg);
|
||||
break;
|
||||
case 9: /* n15,R */
|
||||
s += 2;
|
||||
fprintf(stream, ">$%s,%c", hex16str(get_memw(addr + s - 2)), reg);
|
||||
break;
|
||||
case 11: /* D,R */
|
||||
fprintf(stream, "D,%c", reg);
|
||||
break;
|
||||
case 12: /* n7,PCR */
|
||||
s += 1;
|
||||
fprintf(stream, "<$%s,PCR", hex8str(get_memb(addr + s - 1)));
|
||||
break;
|
||||
case 13: /* n15,PCR */
|
||||
s += 2;
|
||||
fprintf(stream, ">$%s,PCR", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
case 15: /* [n] */
|
||||
s += 2;
|
||||
fprintf(stream, "$%s", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
default:
|
||||
fputs("??", stream);
|
||||
break; }
|
||||
if (pb & 0x10)
|
||||
fputc(']', stream);
|
||||
}
|
||||
break;
|
||||
case 4: /* extended */
|
||||
fprintf(stream, ">$%s", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
case 5: /* inherent */
|
||||
pb = get_memb(addr + 1);
|
||||
switch (d) {
|
||||
case 0x1e: case 0x1f: /* exg tfr */
|
||||
fprintf(stream, "%s,%s", exgi[(pb >> 4) & 0x0f], exgi[pb & 0x0f]);
|
||||
break;
|
||||
case 0x1a: case 0x1c: case 0x3c: /* orcc andcc cwai */
|
||||
fprintf(stream, "#$%s=%s", hex8str(pb), ccstr(pb));
|
||||
break;
|
||||
case 0x34: /* pshs */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (pb & 0x80) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshsregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb <<= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x35: /* puls */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 7; i >= 0; i--) {
|
||||
if (pb & 0x01) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshsregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb >>= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x36: /* pshu */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (pb & 0x80) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshuregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb <<= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x37: /* pulu */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 7; i >= 0; i--) {
|
||||
if (pb & 0x01) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshuregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb >>= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 6: /* relative */
|
||||
{
|
||||
tt_s16 v;
|
||||
|
||||
if (s == 2)
|
||||
v = (tt_s16)(tt_s8)get_memb(addr + 1);
|
||||
else
|
||||
v = (tt_s16)get_memw(addr + s - 2);
|
||||
fprintf(stream, ">$%s", hex16str(addr + (tt_u16)s + v));
|
||||
break;
|
||||
}
|
||||
}
|
||||
fputc('\n', stream);
|
||||
|
||||
return addr + s;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
unsigned int disassemble(unsigned int addr) {
|
||||
int i;
|
||||
int s;
|
||||
int d = get_memb(addr);
|
||||
|
||||
if (d == 0x10)
|
||||
d = get_memb(addr + 1) + 0x100;
|
||||
|
||||
if (d == 0x11)
|
||||
d = get_memb(addr + 1) + 0x200;
|
||||
|
||||
s = size[d];
|
||||
|
||||
log0("%04X ", addr);
|
||||
for (i = 0; i < s; i++) {
|
||||
log0("%02X ", get_memb(addr + i));
|
||||
}
|
||||
log0("\n");
|
||||
return addr + s;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#include "AtomBusMon.h"
|
||||
|
||||
#define OFFSET_REG_A 32
|
||||
#define OFFSET_REG_B 33
|
||||
#define OFFSET_REG_X 34
|
||||
#define OFFSET_REG_Y 36
|
||||
#define OFFSET_REG_U 38
|
||||
#define OFFSET_REG_S 40
|
||||
#define OFFSET_REG_PC 42
|
||||
#define OFFSET_REG_D 44
|
||||
#define OFFSET_REG_CC 45
|
||||
|
||||
char statusString[8] = "EFHINZVC";
|
||||
|
||||
void doCmdRegs(char *params) {
|
||||
int i;
|
||||
unsigned int p = hwRead8(OFFSET_REG_CC);
|
||||
log0("6809 Registers:\n A=%02X B=%02X X=%04X Y=%04X\n",
|
||||
hwRead8(OFFSET_REG_A),
|
||||
hwRead8(OFFSET_REG_B),
|
||||
hwRead16(OFFSET_REG_X),
|
||||
hwRead16(OFFSET_REG_Y));
|
||||
log0(" CC=%02X D=%02X U=%04X S=%04X PC=%04X\n",
|
||||
p,
|
||||
hwRead8(OFFSET_REG_D),
|
||||
hwRead16(OFFSET_REG_U),
|
||||
hwRead16(OFFSET_REG_S),
|
||||
hwRead16(OFFSET_REG_PC));
|
||||
char *sp = statusString;
|
||||
log0(" Status: ");
|
||||
for (i = 0; i <= 7; i++) {
|
||||
log0("%c", ((p & 128) ? (*sp) : '-'));
|
||||
p <<= 1;
|
||||
sp++;
|
||||
}
|
||||
log0("\n");
|
||||
}
|
||||
|
|
@ -92,11 +92,13 @@ architecture behavioral of AtomCpuMon is
|
|||
signal busmon_clk : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(63 downto 0);
|
||||
signal Regs1 : std_logic_vector(255 downto 0);
|
||||
signal memory_rd : std_logic;
|
||||
signal memory_wr : std_logic;
|
||||
signal memory_addr : std_logic_vector(15 downto 0);
|
||||
signal memory_dout : std_logic_vector(7 downto 0);
|
||||
signal memory_din : std_logic_vector(7 downto 0);
|
||||
signal memory_done : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
|
|
@ -107,6 +109,8 @@ begin
|
|||
Phi2 => busmon_clk,
|
||||
Rd_n => not R_W_n_int,
|
||||
Wr_n => R_W_n_int,
|
||||
RdIO_n => '1',
|
||||
WrIO_n => '1',
|
||||
Sync => Sync_int,
|
||||
Rdy => Rdy_int,
|
||||
nRSTin => Res_n,
|
||||
|
|
@ -127,8 +131,7 @@ begin
|
|||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk,
|
||||
Regs(63 downto 0) => Regs,
|
||||
Regs(255 downto 64) => (others <= '0'),
|
||||
Regs => Regs1,
|
||||
RdMemOut=> memory_rd,
|
||||
WrMemOut=> memory_wr,
|
||||
RdIOOut => open,
|
||||
|
|
@ -136,10 +139,12 @@ begin
|
|||
AddrOut => memory_addr,
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din,
|
||||
Done => memory_rd,
|
||||
Done => memory_done,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
Regs1(63 downto 0) <= Regs;
|
||||
Regs1(255 downto 64) <= (others => '0');
|
||||
|
||||
GenT65Core: if UseT65Core generate
|
||||
inst_t65: entity work.T65 port map (
|
||||
|
|
@ -212,6 +217,8 @@ begin
|
|||
Dout when Phi0_c = '1' and R_W_n_int = '0' and memory_rd = '0' else
|
||||
(others => 'Z');
|
||||
|
||||
memory_done <= memory_rd or memory_wr;
|
||||
|
||||
clk_gen : process(clock49)
|
||||
begin
|
||||
if rising_edge(clock49) then
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ architecture behavioral of BusMonCore is
|
|||
|
||||
begin
|
||||
|
||||
inst_dcm5 : entity work.DCM0 port map(
|
||||
inst_dcm0 : entity work.DCM0 port map(
|
||||
CLKIN_IN => clock49,
|
||||
CLK0_OUT => clock_avr,
|
||||
CLK0_OUT1 => open,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.all;
|
||||
|
||||
entity DCM1 is
|
||||
port (CLKIN_IN : in std_logic;
|
||||
CLK0_OUT : out std_logic;
|
||||
CLK0_OUT1 : out std_logic;
|
||||
CLK2X_OUT : out std_logic);
|
||||
end DCM1;
|
||||
|
||||
architecture BEHAVIORAL of DCM1 is
|
||||
signal CLKFX_BUF : std_logic;
|
||||
signal CLKIN_IBUFG : std_logic;
|
||||
signal GND_BIT : std_logic;
|
||||
begin
|
||||
|
||||
GND_BIT <= '0';
|
||||
CLKFX_BUFG_INST : BUFG
|
||||
port map (I => CLKFX_BUF, O => CLK0_OUT);
|
||||
|
||||
DCM_INST : DCM
|
||||
generic map(CLK_FEEDBACK => "NONE",
|
||||
CLKDV_DIVIDE => 4.0, -- 7.3728 =4 9.152 * 3 / 20
|
||||
CLKFX_DIVIDE => 20,
|
||||
CLKFX_MULTIPLY => 3,
|
||||
CLKIN_DIVIDE_BY_2 => false,
|
||||
CLKIN_PERIOD => 20.344,
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => true,
|
||||
FACTORY_JF => x"C080",
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => false)
|
||||
port map (CLKFB => GND_BIT,
|
||||
CLKIN => CLKIN_IN,
|
||||
DSSEN => GND_BIT,
|
||||
PSCLK => GND_BIT,
|
||||
PSEN => GND_BIT,
|
||||
PSINCDEC => GND_BIT,
|
||||
RST => GND_BIT,
|
||||
CLKDV => open,
|
||||
CLKFX => CLKFX_BUF,
|
||||
CLKFX180 => open,
|
||||
CLK0 => open,
|
||||
CLK2X => CLK2X_OUT,
|
||||
CLK2X180 => open,
|
||||
CLK90 => open,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
LOCKED => open,
|
||||
PSDONE => open,
|
||||
STATUS => open);
|
||||
|
||||
end BEHAVIORAL;
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
ADDRESS_MAP avrmap PPC405 0
|
||||
|
||||
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
END_ADDRESS_SPACE;
|
||||
|
||||
END_ADDRESS_MAP;
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||
|
||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
||||
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
||||
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
||||
NET "FIRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6809 pin 4
|
||||
NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 5
|
||||
NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 6
|
||||
#NET "VCC" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6809 pin 7
|
||||
NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 8
|
||||
NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 9
|
||||
NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 10
|
||||
NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 11
|
||||
NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 12
|
||||
NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 13
|
||||
NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 14
|
||||
NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 15
|
||||
NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 16
|
||||
NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 17
|
||||
NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 18
|
||||
NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 19
|
||||
NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 20
|
||||
NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 21
|
||||
NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 22
|
||||
NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 23
|
||||
NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 24
|
||||
NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 25
|
||||
NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 26
|
||||
NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 27
|
||||
NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 28
|
||||
NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 29
|
||||
NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 30
|
||||
NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 31
|
||||
NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 32
|
||||
NET "BUSY" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 33
|
||||
NET "E" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6809 pin 34
|
||||
NET "Q" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6809 pin 35
|
||||
NET "AVMA" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6809 pin 36
|
||||
NET "RES_n" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6809 pin 37
|
||||
NET "LIC" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 38
|
||||
NET "TSC" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6809 pin 39
|
||||
NET "HALT_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6809 pin 40
|
||||
|
||||
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
||||
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
||||
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
||||
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
||||
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
||||
|
||||
# I/O's for test connector
|
||||
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
|
||||
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
|
||||
|
||||
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
||||
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
||||
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
||||
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
||||
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
||||
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
||||
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,247 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2015 David Banks
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ /
|
||||
-- \ \ \/
|
||||
-- \ \
|
||||
-- / / Filename : MC6808ECpuMon.vhd
|
||||
-- /___/ /\ Timestamp : 02/07/2015
|
||||
-- \ \ / \
|
||||
-- \___\/\___\
|
||||
--
|
||||
--Design Name: MC6808ECpuMon
|
||||
--Device: XC3S250E
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.OhoPack.all ;
|
||||
|
||||
entity MC6809ECpuMon is
|
||||
generic (
|
||||
UseCPU09Core : boolean := true
|
||||
);
|
||||
port (
|
||||
clock49 : in std_logic;
|
||||
|
||||
--6809 Signals
|
||||
E : in std_logic;
|
||||
Q : in std_logic;
|
||||
RES_n : inout std_logic;
|
||||
NMI_n : in std_logic;
|
||||
IRQ_n : in std_logic;
|
||||
FIRQ_n : in std_logic;
|
||||
HALT_n : in std_logic;
|
||||
TSC : in std_logic;
|
||||
BS : out std_logic;
|
||||
BA : out std_logic;
|
||||
BUSY : out std_logic;
|
||||
R_W_n : out std_logic;
|
||||
LIC : out std_logic;
|
||||
AVMA : out std_logic;
|
||||
|
||||
Addr : out std_logic_vector(15 downto 0);
|
||||
Data : inout std_logic_vector(7 downto 0);
|
||||
|
||||
-- External trigger inputs
|
||||
trig : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- Serial Console
|
||||
avr_RxD : in std_logic;
|
||||
avr_TxD : out std_logic;
|
||||
|
||||
-- GODIL Switches
|
||||
sw1 : in std_logic;
|
||||
nsw2 : in std_logic;
|
||||
|
||||
-- GODIL LEDs
|
||||
led3 : out std_logic;
|
||||
led6 : out std_logic;
|
||||
led8 : out std_logic;
|
||||
|
||||
-- OHO_DY1 connected to test connector
|
||||
tmosi : out std_logic;
|
||||
tdin : out std_logic;
|
||||
tcclk : out std_logic;
|
||||
|
||||
-- Debugging signals
|
||||
test1 : out std_logic;
|
||||
test2 : out std_logic;
|
||||
test3 : out std_logic;
|
||||
test4 : out std_logic
|
||||
|
||||
);
|
||||
end MC6809ECpuMon;
|
||||
|
||||
architecture behavioral of MC6809ECpuMon is
|
||||
|
||||
signal cpu_clk : std_logic;
|
||||
signal busmon_clk : std_logic;
|
||||
signal R_W_n_int : std_logic;
|
||||
signal LIC_int : std_logic;
|
||||
signal NMI_sync : std_logic;
|
||||
signal IRQ_sync : std_logic;
|
||||
signal FIRQ_sync : std_logic;
|
||||
signal RES_sync : std_logic;
|
||||
signal HALT_sync : std_logic;
|
||||
signal Addr_int : std_logic_vector(15 downto 0);
|
||||
signal Din : std_logic_vector(7 downto 0);
|
||||
signal Dout : std_logic_vector(7 downto 0);
|
||||
signal Sync_int : std_logic;
|
||||
signal Rdy_int : std_logic;
|
||||
|
||||
signal memory_rd : std_logic;
|
||||
signal memory_wr : std_logic;
|
||||
signal memory_addr : std_logic_vector(15 downto 0);
|
||||
signal memory_dout : std_logic_vector(7 downto 0);
|
||||
signal memory_din : std_logic_vector(7 downto 0);
|
||||
signal memory_done : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(111 downto 0);
|
||||
signal Regs1 : std_logic_vector(255 downto 0);
|
||||
|
||||
signal clock7_3728 : std_logic;
|
||||
signal clk_count : std_logic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
inst_dcm1 : entity work.DCM1 port map(
|
||||
CLKIN_IN => clock49,
|
||||
CLK0_OUT => clock7_3728,
|
||||
CLK0_OUT1 => open,
|
||||
CLK2X_OUT => open
|
||||
);
|
||||
|
||||
mon : entity work.BusMonCore
|
||||
generic map (
|
||||
num_comparators => 4
|
||||
)
|
||||
port map (
|
||||
clock49 => clock49,
|
||||
Addr => Addr_int,
|
||||
Data => Data,
|
||||
Phi2 => busmon_clk,
|
||||
Rd_n => not R_W_n_int,
|
||||
Wr_n => R_W_n_int,
|
||||
RdIO_n => '1',
|
||||
WrIO_n => '1',
|
||||
Sync => Sync_int,
|
||||
Rdy => Rdy_int,
|
||||
nRSTin => RES_n,
|
||||
nRSTout => RES_n,
|
||||
CountCycle => Rdy_int,
|
||||
trig => trig,
|
||||
lcd_rs => open,
|
||||
lcd_rw => open,
|
||||
lcd_e => open,
|
||||
lcd_db => open,
|
||||
avr_RxD => avr_RxD,
|
||||
avr_TxD => avr_TxD,
|
||||
sw1 => sw1,
|
||||
nsw2 => nsw2,
|
||||
led3 => led3,
|
||||
led6 => led6,
|
||||
led8 => led8,
|
||||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk,
|
||||
Regs => Regs1,
|
||||
RdMemOut=> memory_rd,
|
||||
WrMemOut=> memory_wr,
|
||||
RdIOOut => open,
|
||||
WrIOOut => open,
|
||||
AddrOut => memory_addr,
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din,
|
||||
Done => memory_done,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
|
||||
Regs1(111 downto 0) <= Regs;
|
||||
Regs1(255 downto 112) <= (others => '0');
|
||||
|
||||
GenCPU09Core: if UseCPU09Core generate
|
||||
inst_cpu09: entity work.cpu09 port map (
|
||||
clk => cpu_clk,
|
||||
rst => RES_sync,
|
||||
vma => AVMA,
|
||||
lic_out => LIC_int,
|
||||
ifetch => open,
|
||||
opfetch => open,
|
||||
ba => BA,
|
||||
bs => BS,
|
||||
addr => Addr_int,
|
||||
rw => R_W_n_int,
|
||||
data_out => Dout,
|
||||
data_in => Din,
|
||||
irq => IRQ_sync,
|
||||
firq => FIRQ_sync,
|
||||
nmi => NMI_sync,
|
||||
halt => HALT_sync,
|
||||
hold => not RDY_int,
|
||||
Regs => Regs
|
||||
);
|
||||
end generate;
|
||||
|
||||
clk_gen : process(clock7_3728)
|
||||
begin
|
||||
if rising_edge(clock7_3728) then
|
||||
clk_count <= clk_count + 1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
irq_gen : process(cpu_clk)
|
||||
begin
|
||||
if falling_edge(cpu_clk) then
|
||||
NMI_sync <= not NMI_n;
|
||||
IRQ_sync <= not IRQ_n;
|
||||
FIRQ_sync <= not FIRQ_n;
|
||||
RES_sync <= not RES_n;
|
||||
HALT_sync <= not HALT_n;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sync_gen : process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if (RDY_int = '1') then
|
||||
Sync_int <= LIC_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_clk <= not E;
|
||||
busmon_clk <= E;
|
||||
|
||||
R_W_n <= 'Z' when TSC = '1' else
|
||||
'1' when memory_rd = '1' else
|
||||
'0' when memory_wr = '1' else
|
||||
R_W_n_int;
|
||||
|
||||
Addr <= (others => 'Z') when TSC = '1' else
|
||||
memory_addr when (memory_rd = '1' or memory_wr = '1') else
|
||||
Addr_int;
|
||||
|
||||
Din <= Data;
|
||||
memory_din <= Data;
|
||||
|
||||
Data <= memory_dout when TSC = '0' and E = '1' and memory_wr = '1' else
|
||||
Dout when TSC = '0' and E = '1' and R_W_n_int = '0' and memory_rd = '0' else
|
||||
(others => 'Z');
|
||||
|
||||
memory_done <= memory_rd or memory_wr;
|
||||
|
||||
BUSY <= '0';
|
||||
LIC <= LIC_int;
|
||||
|
||||
test1 <= Sync_int;
|
||||
test2 <= RDY_int;
|
||||
test3 <= LIC_int;
|
||||
test4 <= clk_count(1);
|
||||
|
||||
end behavioral;
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue