mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-12-21 09:29:52 +00:00
Initial checkin of ICE-6809; version now 0.49
Change-Id: I502840a0be0fa58adfc9ddb27c4e2a35a7c2849c
This commit is contained in:
David Banks
parent
10be34c618
commit
20269623ea
1
.gitignore
vendored
1
.gitignore
vendored
@ -7,6 +7,7 @@ src/AtomBusMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/Z80CpuMon_bd.bmm
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src/MC6809ECpuMon_bd.bmm
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*~
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#*
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firmware/*.o
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5406
6809/ExBasROM.LST
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6809/ExBasROM.LST
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Load Diff
5398
6809/ExBasROM.asm
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5398
6809/ExBasROM.asm
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Load Diff
BIN
6809/ExBasROM.bin
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BIN
6809/ExBasROM.bin
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513
6809/ExBasROM.hex
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513
6809/ExBasROM.hex
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
:00000001FF
|
||||
564
MC6809ECpuMon.xise
Normal file
564
MC6809ECpuMon.xise
Normal file
@ -0,0 +1,564 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
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|
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
|
||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
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||||
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|
||||
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
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||||
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|
||||
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|
||||
</file>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
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|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Memory/XDM4Kx8.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Memory/XPM8Kx16.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerLatch.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
|
||||
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|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/SYS09/cpu09l.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/MC6809ECpuMon.bmm" xil_pn:type="FILE_BMM">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/DCM/DCM1.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MC6809ECpuMon|behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/MC6809ECpuMon.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MC6809ECpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MC6809ECpuMon_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="MC6809ECpuMon_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MC6809ECpuMon_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MC6809ECpuMon_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="MC6809ECpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-23T12:17:55" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="614C752717807585A7E3847C608873AC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/MC6809ECpuMon" xil_pn:name="src/MC6809ECpuMon.ucf"/>
|
||||
<binding xil_pn:location="/MC6809EECpuMon" xil_pn:name="src/MC6809ECpuMon.bmm"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@ -10,12 +10,14 @@
|
||||
* VERSION and NAME are used in the start-up message
|
||||
********************************************************/
|
||||
|
||||
#define VERSION "0.48"
|
||||
#define VERSION "0.49"
|
||||
|
||||
#if (CPU == Z80)
|
||||
#define NAME "ICE-T80"
|
||||
#elif (CPU == 6502)
|
||||
#define NAME "ICE-T65"
|
||||
#elif (CPU == 6809)
|
||||
#define NAME "ICE-6809"
|
||||
#else
|
||||
#error "Unsupported CPU type"
|
||||
#endif
|
||||
@ -276,7 +278,7 @@ void (*cmdFuncs[NUM_CMDS])(char *params) = {
|
||||
********************************************************/
|
||||
|
||||
// The space available for address comparators depends on the size of the CPU core
|
||||
#if (CPU == Z80)
|
||||
#if ((CPU == Z80) || (CPU == 6809))
|
||||
#define MAXBKPTS 4
|
||||
#else
|
||||
#define MAXBKPTS 8
|
||||
|
||||
52
firmware/Makefile.6809cpu
Normal file
52
firmware/Makefile.6809cpu
Normal file
@ -0,0 +1,52 @@
|
||||
# Paths that will need changing
|
||||
|
||||
ATOMFPGA=$(HOME)/atom/AtomBusMon
|
||||
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
|
||||
XILINX=/opt/Xilinx/14.7
|
||||
|
||||
# Shouldn't need to make changes below this point
|
||||
|
||||
BIT_FILE=$(ATOMFPGA)/working/MC6809ECpuMon.bit
|
||||
BMM_FILE=$(ATOMFPGA)/src/MC6809ECpuMon_bd.bmm
|
||||
|
||||
|
||||
# Papilio dev environment
|
||||
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
|
||||
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
|
||||
SREC_CAT=srec_cat
|
||||
GAWK=gawk
|
||||
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem
|
||||
|
||||
# AVR dev environment
|
||||
MCU=atmega103
|
||||
F_CPU=15855484
|
||||
CC=avr-gcc
|
||||
OBJCOPY=avr-objcopy
|
||||
|
||||
CFLAGS=-DCPU=6809 -DCPUEMBEDDED -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues -mno-interrupts
|
||||
|
||||
OBJECTS=AtomBusMon.o dis6809.o regs6809.o status.o
|
||||
|
||||
build: avr6809cpu.bit
|
||||
|
||||
avr6809cpu.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr6809cpu.bit
|
||||
|
||||
avr_progmem.mem: avr_progmem.hex
|
||||
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
|
||||
$(GAWK) ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
|
||||
rm tmp.mem
|
||||
|
||||
avr_progmem.hex : avr_progmem.out
|
||||
$(OBJCOPY) -R .eeprom -O ihex avr_progmem.out avr_progmem.hex
|
||||
avr_progmem.out : $(OBJECTS)
|
||||
$(CC) $(CFLAGS) -o avr_progmem.out -Wl,-Map,avr_progmem.map $^
|
||||
%.o : %.c
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
%.o : %.S
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
|
||||
.phony: clean
|
||||
|
||||
clean:
|
||||
rm -f avr6809cpu.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
||||
487
firmware/dis6809.c
Normal file
487
firmware/dis6809.c
Normal file
@ -0,0 +1,487 @@
|
||||
/* dis6809.c -- 6809 disassembler
|
||||
Copyright (C) 1998 Jerome Thoen
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
|
||||
#include "AtomBusMon.h"
|
||||
|
||||
static const int size[] = {
|
||||
2,1,1,2,2,1,2,2,2,2,2,1,2,2,2,2,
|
||||
1,1,1,1,1,1,3,3,1,1,2,1,2,1,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,1,1,1,1,2,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
2,1,1,2,2,1,2,2,2,2,2,1,2,2,2,2,
|
||||
3,1,1,3,3,1,3,3,3,3,3,1,3,3,3,3,
|
||||
2,2,2,3,2,2,2,1,2,2,2,2,3,2,3,1,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
2,2,2,3,2,2,2,1,2,2,2,2,3,1,3,1,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,2,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,4,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,3,3,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,3,3,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,4,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,3,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,3,3,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,4,4,
|
||||
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,2,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,1,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,1,1,
|
||||
1,1,1,3,1,1,1,1,1,1,1,1,3,1,1,1,
|
||||
1,1,1,4,1,1,1,1,1,1,1,1,4,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 };
|
||||
|
||||
unsigned char get_memb(unsigned int addr) {
|
||||
loadAddr(addr);
|
||||
return readMemByteInc();
|
||||
}
|
||||
|
||||
#ifdef FULLDISASSEMBLER
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
typedef unsigned char tt_u8;
|
||||
typedef signed char tt_s8;
|
||||
typedef unsigned short tt_u16;
|
||||
typedef signed short tt_s16;
|
||||
|
||||
|
||||
unsigned int get_memw(unsigned int addr) {
|
||||
loadAddr(addr);
|
||||
return readMemByteInc() + (readMemByteInc() << 8);
|
||||
}
|
||||
|
||||
/*
|
||||
modes:
|
||||
1 immediate
|
||||
2 direct
|
||||
3 indexed
|
||||
4 extended
|
||||
5 inherent
|
||||
6 relative
|
||||
*/
|
||||
|
||||
static const int mode[] = {
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
0,0,5,5,0,0,6,6,0,5,5,0,5,5,5,5,
|
||||
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
|
||||
3,3,3,3,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,6,1,0,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,
|
||||
2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,
|
||||
3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
|
||||
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
|
||||
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,1,0,0,0,0,0,0,0,0,1,0,1,0,
|
||||
0,0,0,2,0,0,0,0,0,0,0,0,2,0,2,2,
|
||||
0,0,0,3,0,0,0,0,0,0,0,0,3,0,3,3,
|
||||
0,0,0,4,0,0,0,0,0,0,0,0,4,0,4,4,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,4,
|
||||
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,
|
||||
0,0,0,2,0,0,0,0,0,0,0,0,2,0,0,0,
|
||||
0,0,0,3,0,0,0,0,0,0,0,0,3,0,0,0,
|
||||
0,0,0,4,0,0,0,0,0,0,0,0,4,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
|
||||
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
|
||||
|
||||
|
||||
static const char inst[] = "\
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
-- -- NOP SYNC?? ?? LBRALBSR?? DAA ORCC?? ANDCSEX EXG TFR \
|
||||
BRA BRN BHI BLS BCC BLO BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE \
|
||||
LEAXLEAYLEASLEAUPSHSPULSPSHUPULU?? RTS ABX RTI CWAIMUL ?? SWI \
|
||||
NEGA?? ?? COMALSRA?? RORAASRAASLAROLADECA?? INCATSTA?? CLRA\
|
||||
NEGB?? ?? COMBLSRB?? RORBASRBLSLBROLBDECB?? INCBTSTB?? CLRB\
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
NEG ?? ?? COM LSR ?? ROR ASR ASL ROL DEC ?? INC TST JMP CLR \
|
||||
SUBACMPASBCASUBDANDABITALDA ?? EORAADCAORA ADDACMPXBSR LDX ?? \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBACMPASBCASUBDANDABITALDA STA EORAADCAORA ADDACMPXJSR LDX STX \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB ?? EORBADCBORB ADDBLDD ?? LDU ?? \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
SUBBCMPBSBCBADDDANDBBITBLDB STB EORBADCBORB ADDBLDD STD LDU STU \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? LBRNLBHILBLSLBCCLBLOLBNELBEQLBVCLBVSLBPLLBMILBGELBLTLBGTLBLE\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? SWI2\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY ?? \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? CMPD?? ?? ?? ?? ?? ?? ?? ?? CMPY?? LDY STY \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? LDS STS \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? SWI3\
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? CMPU?? ?? ?? ?? ?? ?? ?? ?? CMPS?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? \
|
||||
?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ";
|
||||
|
||||
static const char regi[] = { 'X', 'Y', 'U', 'S' };
|
||||
|
||||
static const char *exgi[] = { "D", "X", "Y", "U", "S", "PC", "??", "??", "A",
|
||||
"B", "CC", "DP", "??", "??", "??", "??" };
|
||||
|
||||
static const char *pshsregi[] = { "PC", "U", "Y", "X", "DP", "B", "A", "CC" };
|
||||
static const char *pshuregi[] = { "PC", "S", "Y", "X", "DP", "B", "A", "CC" };
|
||||
|
||||
/* disassemble one instruction at adress adr and return its size */
|
||||
|
||||
char hexdigit(tt_u16 v)
|
||||
{
|
||||
v &= 0xf;
|
||||
if (v <= 9)
|
||||
return '0' + v;
|
||||
else
|
||||
return 'A' - 10 + v;
|
||||
}
|
||||
|
||||
char *hex8str(tt_u8 v)
|
||||
{
|
||||
static char tmpbuf[3] = " ";
|
||||
|
||||
tmpbuf[1] = hexdigit(v);
|
||||
tmpbuf[0] = hexdigit(v >> 4);
|
||||
|
||||
return tmpbuf;
|
||||
}
|
||||
|
||||
char *hex16str(tt_u16 v)
|
||||
{
|
||||
static char tmpbuf[5] = " ";
|
||||
|
||||
tmpbuf[3] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[2] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[1] = hexdigit(v);
|
||||
v >>= 4;
|
||||
tmpbuf[0] = hexdigit(v);
|
||||
|
||||
return tmpbuf;
|
||||
}
|
||||
|
||||
static const char ccbits[] = "EFHINZVC";
|
||||
|
||||
char *ccstr(tt_u8 val)
|
||||
{
|
||||
static char tempbuf[9] = " ";
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (val & 0x80)
|
||||
tempbuf[i] = ccbits[i];
|
||||
else
|
||||
tempbuf[i] = '.';
|
||||
val <<= 1;
|
||||
}
|
||||
|
||||
return tempbuf;
|
||||
}
|
||||
|
||||
unsigned int disassemble(unsigned int addr)
|
||||
{
|
||||
int d = get_memb(addr);
|
||||
int s, i;
|
||||
tt_u8 pb;
|
||||
char reg;
|
||||
|
||||
FILE *stream = &ser0stream;
|
||||
|
||||
fprintf(stream, "%04hX: %04hX %04hX ", addr, get_memw(addr), get_memw(addr + 2));
|
||||
|
||||
if (d == 0x10)
|
||||
d = get_memb(addr + 1) + 0x100;
|
||||
|
||||
if (d == 0x11)
|
||||
d = get_memb(addr + 1) + 0x200;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
fputc(inst[d * 4 + i], stream);
|
||||
|
||||
fputs(" ", stream);
|
||||
|
||||
s = size[d];
|
||||
|
||||
switch(mode[d]) {
|
||||
case 1: /* immediate */
|
||||
fputs("#$", stream);
|
||||
if (s == 2)
|
||||
fputs(hex8str(get_memb(addr + 1)), stream);
|
||||
else
|
||||
fputs(hex16str(get_memw(addr + s - 2)), stream);
|
||||
break;
|
||||
case 2: /* direct */
|
||||
fputs("<$", stream);
|
||||
fputs(hex8str(get_memb(addr + s - 1)), stream);
|
||||
break;
|
||||
case 3: /* indexed */
|
||||
pb = get_memb(addr + s - 1);
|
||||
reg = regi[(pb >> 5) & 0x03];
|
||||
|
||||
if (!(pb & 0x80)) { /* n4,R */
|
||||
if (pb & 0x10)
|
||||
fprintf(stream, "-$%s,%c", hex8str(((pb & 0x0f) ^ 0x0f) + 1), reg);
|
||||
else
|
||||
fprintf(stream, "$%s,%c", hex8str(pb & 0x0f), reg);
|
||||
}
|
||||
else {
|
||||
if (pb & 0x10)
|
||||
fputc('[', stream);
|
||||
switch (pb & 0x0f) {
|
||||
case 0: /* ,R+ */
|
||||
fprintf(stream, ",%c+", reg);
|
||||
break;
|
||||
case 1: /* ,R++ */
|
||||
fprintf(stream, ",%c++", reg);
|
||||
break;
|
||||
case 2: /* ,-R */
|
||||
fprintf(stream, ",-%c", reg);
|
||||
break;
|
||||
case 3: /* ,--R */
|
||||
fprintf(stream, ",--%c", reg);
|
||||
break;
|
||||
case 4: /* ,R */
|
||||
fprintf(stream, ",%c", reg);
|
||||
break;
|
||||
case 5: /* B,R */
|
||||
fprintf(stream, "B,%c", reg);
|
||||
break;
|
||||
case 6: /* A,R */
|
||||
fprintf(stream, "A,%c", reg);
|
||||
break;
|
||||
case 8: /* n7,R */
|
||||
s += 1;
|
||||
fprintf(stream, "<$%s,%c", hex8str(get_memb(addr + s - 1)), reg);
|
||||
break;
|
||||
case 9: /* n15,R */
|
||||
s += 2;
|
||||
fprintf(stream, ">$%s,%c", hex16str(get_memw(addr + s - 2)), reg);
|
||||
break;
|
||||
case 11: /* D,R */
|
||||
fprintf(stream, "D,%c", reg);
|
||||
break;
|
||||
case 12: /* n7,PCR */
|
||||
s += 1;
|
||||
fprintf(stream, "<$%s,PCR", hex8str(get_memb(addr + s - 1)));
|
||||
break;
|
||||
case 13: /* n15,PCR */
|
||||
s += 2;
|
||||
fprintf(stream, ">$%s,PCR", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
case 15: /* [n] */
|
||||
s += 2;
|
||||
fprintf(stream, "$%s", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
default:
|
||||
fputs("??", stream);
|
||||
break; }
|
||||
if (pb & 0x10)
|
||||
fputc(']', stream);
|
||||
}
|
||||
break;
|
||||
case 4: /* extended */
|
||||
fprintf(stream, ">$%s", hex16str(get_memw(addr + s - 2)));
|
||||
break;
|
||||
case 5: /* inherent */
|
||||
pb = get_memb(addr + 1);
|
||||
switch (d) {
|
||||
case 0x1e: case 0x1f: /* exg tfr */
|
||||
fprintf(stream, "%s,%s", exgi[(pb >> 4) & 0x0f], exgi[pb & 0x0f]);
|
||||
break;
|
||||
case 0x1a: case 0x1c: case 0x3c: /* orcc andcc cwai */
|
||||
fprintf(stream, "#$%s=%s", hex8str(pb), ccstr(pb));
|
||||
break;
|
||||
case 0x34: /* pshs */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (pb & 0x80) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshsregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb <<= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x35: /* puls */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 7; i >= 0; i--) {
|
||||
if (pb & 0x01) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshsregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb >>= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x36: /* pshu */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (pb & 0x80) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshuregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb <<= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x37: /* pulu */
|
||||
{
|
||||
int p = 0;
|
||||
|
||||
for (i = 7; i >= 0; i--) {
|
||||
if (pb & 0x01) {
|
||||
if (p)
|
||||
fputc(',', stream);
|
||||
fputs(pshuregi[i], stream);
|
||||
p = 1;
|
||||
}
|
||||
pb >>= 1;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 6: /* relative */
|
||||
{
|
||||
tt_s16 v;
|
||||
|
||||
if (s == 2)
|
||||
v = (tt_s16)(tt_s8)get_memb(addr + 1);
|
||||
else
|
||||
v = (tt_s16)get_memw(addr + s - 2);
|
||||
fprintf(stream, ">$%s", hex16str(addr + (tt_u16)s + v));
|
||||
break;
|
||||
}
|
||||
}
|
||||
fputc('\n', stream);
|
||||
|
||||
return addr + s;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
unsigned int disassemble(unsigned int addr) {
|
||||
int i;
|
||||
int s;
|
||||
int d = get_memb(addr);
|
||||
|
||||
if (d == 0x10)
|
||||
d = get_memb(addr + 1) + 0x100;
|
||||
|
||||
if (d == 0x11)
|
||||
d = get_memb(addr + 1) + 0x200;
|
||||
|
||||
s = size[d];
|
||||
|
||||
log0("%04X ", addr);
|
||||
for (i = 0; i < s; i++) {
|
||||
log0("%02X ", get_memb(addr + i));
|
||||
}
|
||||
log0("\n");
|
||||
return addr + s;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
37
firmware/regs6809.c
Normal file
37
firmware/regs6809.c
Normal file
@ -0,0 +1,37 @@
|
||||
#include "AtomBusMon.h"
|
||||
|
||||
#define OFFSET_REG_A 32
|
||||
#define OFFSET_REG_B 33
|
||||
#define OFFSET_REG_X 34
|
||||
#define OFFSET_REG_Y 36
|
||||
#define OFFSET_REG_U 38
|
||||
#define OFFSET_REG_S 40
|
||||
#define OFFSET_REG_PC 42
|
||||
#define OFFSET_REG_D 44
|
||||
#define OFFSET_REG_CC 45
|
||||
|
||||
char statusString[8] = "EFHINZVC";
|
||||
|
||||
void doCmdRegs(char *params) {
|
||||
int i;
|
||||
unsigned int p = hwRead8(OFFSET_REG_CC);
|
||||
log0("6809 Registers:\n A=%02X B=%02X X=%04X Y=%04X\n",
|
||||
hwRead8(OFFSET_REG_A),
|
||||
hwRead8(OFFSET_REG_B),
|
||||
hwRead16(OFFSET_REG_X),
|
||||
hwRead16(OFFSET_REG_Y));
|
||||
log0(" CC=%02X D=%02X U=%04X S=%04X PC=%04X\n",
|
||||
p,
|
||||
hwRead8(OFFSET_REG_D),
|
||||
hwRead16(OFFSET_REG_U),
|
||||
hwRead16(OFFSET_REG_S),
|
||||
hwRead16(OFFSET_REG_PC));
|
||||
char *sp = statusString;
|
||||
log0(" Status: ");
|
||||
for (i = 0; i <= 7; i++) {
|
||||
log0("%c", ((p & 128) ? (*sp) : '-'));
|
||||
p <<= 1;
|
||||
sp++;
|
||||
}
|
||||
log0("\n");
|
||||
}
|
||||
@ -92,11 +92,13 @@ architecture behavioral of AtomCpuMon is
|
||||
signal busmon_clk : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(63 downto 0);
|
||||
signal Regs1 : std_logic_vector(255 downto 0);
|
||||
signal memory_rd : std_logic;
|
||||
signal memory_wr : std_logic;
|
||||
signal memory_addr : std_logic_vector(15 downto 0);
|
||||
signal memory_dout : std_logic_vector(7 downto 0);
|
||||
signal memory_din : std_logic_vector(7 downto 0);
|
||||
signal memory_done : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
@ -107,6 +109,8 @@ begin
|
||||
Phi2 => busmon_clk,
|
||||
Rd_n => not R_W_n_int,
|
||||
Wr_n => R_W_n_int,
|
||||
RdIO_n => '1',
|
||||
WrIO_n => '1',
|
||||
Sync => Sync_int,
|
||||
Rdy => Rdy_int,
|
||||
nRSTin => Res_n,
|
||||
@ -127,8 +131,7 @@ begin
|
||||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk,
|
||||
Regs(63 downto 0) => Regs,
|
||||
Regs(255 downto 64) => (others <= '0'),
|
||||
Regs => Regs1,
|
||||
RdMemOut=> memory_rd,
|
||||
WrMemOut=> memory_wr,
|
||||
RdIOOut => open,
|
||||
@ -136,10 +139,12 @@ begin
|
||||
AddrOut => memory_addr,
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din,
|
||||
Done => memory_rd,
|
||||
Done => memory_done,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
Regs1(63 downto 0) <= Regs;
|
||||
Regs1(255 downto 64) <= (others => '0');
|
||||
|
||||
GenT65Core: if UseT65Core generate
|
||||
inst_t65: entity work.T65 port map (
|
||||
@ -212,6 +217,8 @@ begin
|
||||
Dout when Phi0_c = '1' and R_W_n_int = '0' and memory_rd = '0' else
|
||||
(others => 'Z');
|
||||
|
||||
memory_done <= memory_rd or memory_wr;
|
||||
|
||||
clk_gen : process(clock49)
|
||||
begin
|
||||
if rising_edge(clock49) then
|
||||
|
||||
@ -152,7 +152,7 @@ architecture behavioral of BusMonCore is
|
||||
|
||||
begin
|
||||
|
||||
inst_dcm5 : entity work.DCM0 port map(
|
||||
inst_dcm0 : entity work.DCM0 port map(
|
||||
CLKIN_IN => clock49,
|
||||
CLK0_OUT => clock_avr,
|
||||
CLK0_OUT1 => open,
|
||||
|
||||
59
src/DCM/DCM1.vhd
Normal file
59
src/DCM/DCM1.vhd
Normal file
@ -0,0 +1,59 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
library UNISIM;
|
||||
use UNISIM.Vcomponents.all;
|
||||
|
||||
entity DCM1 is
|
||||
port (CLKIN_IN : in std_logic;
|
||||
CLK0_OUT : out std_logic;
|
||||
CLK0_OUT1 : out std_logic;
|
||||
CLK2X_OUT : out std_logic);
|
||||
end DCM1;
|
||||
|
||||
architecture BEHAVIORAL of DCM1 is
|
||||
signal CLKFX_BUF : std_logic;
|
||||
signal CLKIN_IBUFG : std_logic;
|
||||
signal GND_BIT : std_logic;
|
||||
begin
|
||||
|
||||
GND_BIT <= '0';
|
||||
CLKFX_BUFG_INST : BUFG
|
||||
port map (I => CLKFX_BUF, O => CLK0_OUT);
|
||||
|
||||
DCM_INST : DCM
|
||||
generic map(CLK_FEEDBACK => "NONE",
|
||||
CLKDV_DIVIDE => 4.0, -- 7.3728 =4 9.152 * 3 / 20
|
||||
CLKFX_DIVIDE => 20,
|
||||
CLKFX_MULTIPLY => 3,
|
||||
CLKIN_DIVIDE_BY_2 => false,
|
||||
CLKIN_PERIOD => 20.344,
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
DFS_FREQUENCY_MODE => "LOW",
|
||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => true,
|
||||
FACTORY_JF => x"C080",
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => false)
|
||||
port map (CLKFB => GND_BIT,
|
||||
CLKIN => CLKIN_IN,
|
||||
DSSEN => GND_BIT,
|
||||
PSCLK => GND_BIT,
|
||||
PSEN => GND_BIT,
|
||||
PSINCDEC => GND_BIT,
|
||||
RST => GND_BIT,
|
||||
CLKDV => open,
|
||||
CLKFX => CLKFX_BUF,
|
||||
CLKFX180 => open,
|
||||
CLK0 => open,
|
||||
CLK2X => CLK2X_OUT,
|
||||
CLK2X180 => open,
|
||||
CLK90 => open,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
LOCKED => open,
|
||||
PSDONE => open,
|
||||
STATUS => open);
|
||||
|
||||
end BEHAVIORAL;
|
||||
38
src/MC6809ECpuMon.bmm
Normal file
38
src/MC6809ECpuMon.bmm
Normal file
@ -0,0 +1,38 @@
|
||||
ADDRESS_MAP avrmap PPC405 0
|
||||
|
||||
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
END_ADDRESS_SPACE;
|
||||
|
||||
END_ADDRESS_MAP;
|
||||
83
src/MC6809ECpuMon.ucf
Normal file
83
src/MC6809ECpuMon.ucf
Normal file
@ -0,0 +1,83 @@
|
||||
NET "E" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "clock49" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||
|
||||
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6809 pin 1
|
||||
NET "NMI_n" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6809 pin 2
|
||||
NET "IRQ_n" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6809 pin 3
|
||||
NET "FIRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6809 pin 4
|
||||
NET "BS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 5
|
||||
NET "BA" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 6
|
||||
#NET "VCC" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6809 pin 7
|
||||
NET "Addr<0>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 8
|
||||
NET "Addr<1>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 9
|
||||
NET "Addr<2>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 10
|
||||
NET "Addr<3>" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 11
|
||||
NET "Addr<4>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 12
|
||||
NET "Addr<5>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 13
|
||||
NET "Addr<6>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 14
|
||||
NET "Addr<7>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 15
|
||||
NET "Addr<8>" LOC="P54" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 16
|
||||
NET "Addr<9>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 17
|
||||
NET "Addr<10>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 18
|
||||
NET "Addr<11>" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 19
|
||||
NET "Addr<12>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 20
|
||||
NET "Addr<13>" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 21
|
||||
NET "Addr<14>" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 22
|
||||
NET "Addr<15>" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 23
|
||||
NET "Data<7>" LOC="P71" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 24
|
||||
NET "Data<6>" LOC="P86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 25
|
||||
NET "Data<5>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 26
|
||||
NET "Data<4>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 27
|
||||
NET "Data<3>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 28
|
||||
NET "Data<2>" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 29
|
||||
NET "Data<1>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 30
|
||||
NET "Data<0>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 31
|
||||
NET "R_W_n" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 32
|
||||
NET "BUSY" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 33
|
||||
NET "E" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6809 pin 34
|
||||
NET "Q" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6809 pin 35
|
||||
NET "AVMA" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6809 pin 36
|
||||
NET "RES_n" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6809 pin 37
|
||||
NET "LIC" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; # 6809 pin 38
|
||||
NET "TSC" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6809 pin 39
|
||||
NET "HALT_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6809 pin 40
|
||||
|
||||
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
||||
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
||||
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
||||
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
||||
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
||||
|
||||
# I/O's for test connector
|
||||
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
|
||||
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
|
||||
|
||||
|
||||
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
||||
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
||||
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
||||
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
||||
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
||||
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
||||
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
||||
|
||||
|
||||
|
||||
247
src/MC6809ECpuMon.vhd
Normal file
247
src/MC6809ECpuMon.vhd
Normal file
@ -0,0 +1,247 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2015 David Banks
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ /
|
||||
-- \ \ \/
|
||||
-- \ \
|
||||
-- / / Filename : MC6808ECpuMon.vhd
|
||||
-- /___/ /\ Timestamp : 02/07/2015
|
||||
-- \ \ / \
|
||||
-- \___\/\___\
|
||||
--
|
||||
--Design Name: MC6808ECpuMon
|
||||
--Device: XC3S250E
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.OhoPack.all ;
|
||||
|
||||
entity MC6809ECpuMon is
|
||||
generic (
|
||||
UseCPU09Core : boolean := true
|
||||
);
|
||||
port (
|
||||
clock49 : in std_logic;
|
||||
|
||||
--6809 Signals
|
||||
E : in std_logic;
|
||||
Q : in std_logic;
|
||||
RES_n : inout std_logic;
|
||||
NMI_n : in std_logic;
|
||||
IRQ_n : in std_logic;
|
||||
FIRQ_n : in std_logic;
|
||||
HALT_n : in std_logic;
|
||||
TSC : in std_logic;
|
||||
BS : out std_logic;
|
||||
BA : out std_logic;
|
||||
BUSY : out std_logic;
|
||||
R_W_n : out std_logic;
|
||||
LIC : out std_logic;
|
||||
AVMA : out std_logic;
|
||||
|
||||
Addr : out std_logic_vector(15 downto 0);
|
||||
Data : inout std_logic_vector(7 downto 0);
|
||||
|
||||
-- External trigger inputs
|
||||
trig : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- Serial Console
|
||||
avr_RxD : in std_logic;
|
||||
avr_TxD : out std_logic;
|
||||
|
||||
-- GODIL Switches
|
||||
sw1 : in std_logic;
|
||||
nsw2 : in std_logic;
|
||||
|
||||
-- GODIL LEDs
|
||||
led3 : out std_logic;
|
||||
led6 : out std_logic;
|
||||
led8 : out std_logic;
|
||||
|
||||
-- OHO_DY1 connected to test connector
|
||||
tmosi : out std_logic;
|
||||
tdin : out std_logic;
|
||||
tcclk : out std_logic;
|
||||
|
||||
-- Debugging signals
|
||||
test1 : out std_logic;
|
||||
test2 : out std_logic;
|
||||
test3 : out std_logic;
|
||||
test4 : out std_logic
|
||||
|
||||
);
|
||||
end MC6809ECpuMon;
|
||||
|
||||
architecture behavioral of MC6809ECpuMon is
|
||||
|
||||
signal cpu_clk : std_logic;
|
||||
signal busmon_clk : std_logic;
|
||||
signal R_W_n_int : std_logic;
|
||||
signal LIC_int : std_logic;
|
||||
signal NMI_sync : std_logic;
|
||||
signal IRQ_sync : std_logic;
|
||||
signal FIRQ_sync : std_logic;
|
||||
signal RES_sync : std_logic;
|
||||
signal HALT_sync : std_logic;
|
||||
signal Addr_int : std_logic_vector(15 downto 0);
|
||||
signal Din : std_logic_vector(7 downto 0);
|
||||
signal Dout : std_logic_vector(7 downto 0);
|
||||
signal Sync_int : std_logic;
|
||||
signal Rdy_int : std_logic;
|
||||
|
||||
signal memory_rd : std_logic;
|
||||
signal memory_wr : std_logic;
|
||||
signal memory_addr : std_logic_vector(15 downto 0);
|
||||
signal memory_dout : std_logic_vector(7 downto 0);
|
||||
signal memory_din : std_logic_vector(7 downto 0);
|
||||
signal memory_done : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(111 downto 0);
|
||||
signal Regs1 : std_logic_vector(255 downto 0);
|
||||
|
||||
signal clock7_3728 : std_logic;
|
||||
signal clk_count : std_logic_vector(1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
inst_dcm1 : entity work.DCM1 port map(
|
||||
CLKIN_IN => clock49,
|
||||
CLK0_OUT => clock7_3728,
|
||||
CLK0_OUT1 => open,
|
||||
CLK2X_OUT => open
|
||||
);
|
||||
|
||||
mon : entity work.BusMonCore
|
||||
generic map (
|
||||
num_comparators => 4
|
||||
)
|
||||
port map (
|
||||
clock49 => clock49,
|
||||
Addr => Addr_int,
|
||||
Data => Data,
|
||||
Phi2 => busmon_clk,
|
||||
Rd_n => not R_W_n_int,
|
||||
Wr_n => R_W_n_int,
|
||||
RdIO_n => '1',
|
||||
WrIO_n => '1',
|
||||
Sync => Sync_int,
|
||||
Rdy => Rdy_int,
|
||||
nRSTin => RES_n,
|
||||
nRSTout => RES_n,
|
||||
CountCycle => Rdy_int,
|
||||
trig => trig,
|
||||
lcd_rs => open,
|
||||
lcd_rw => open,
|
||||
lcd_e => open,
|
||||
lcd_db => open,
|
||||
avr_RxD => avr_RxD,
|
||||
avr_TxD => avr_TxD,
|
||||
sw1 => sw1,
|
||||
nsw2 => nsw2,
|
||||
led3 => led3,
|
||||
led6 => led6,
|
||||
led8 => led8,
|
||||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk,
|
||||
Regs => Regs1,
|
||||
RdMemOut=> memory_rd,
|
||||
WrMemOut=> memory_wr,
|
||||
RdIOOut => open,
|
||||
WrIOOut => open,
|
||||
AddrOut => memory_addr,
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din,
|
||||
Done => memory_done,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
|
||||
Regs1(111 downto 0) <= Regs;
|
||||
Regs1(255 downto 112) <= (others => '0');
|
||||
|
||||
GenCPU09Core: if UseCPU09Core generate
|
||||
inst_cpu09: entity work.cpu09 port map (
|
||||
clk => cpu_clk,
|
||||
rst => RES_sync,
|
||||
vma => AVMA,
|
||||
lic_out => LIC_int,
|
||||
ifetch => open,
|
||||
opfetch => open,
|
||||
ba => BA,
|
||||
bs => BS,
|
||||
addr => Addr_int,
|
||||
rw => R_W_n_int,
|
||||
data_out => Dout,
|
||||
data_in => Din,
|
||||
irq => IRQ_sync,
|
||||
firq => FIRQ_sync,
|
||||
nmi => NMI_sync,
|
||||
halt => HALT_sync,
|
||||
hold => not RDY_int,
|
||||
Regs => Regs
|
||||
);
|
||||
end generate;
|
||||
|
||||
clk_gen : process(clock7_3728)
|
||||
begin
|
||||
if rising_edge(clock7_3728) then
|
||||
clk_count <= clk_count + 1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
irq_gen : process(cpu_clk)
|
||||
begin
|
||||
if falling_edge(cpu_clk) then
|
||||
NMI_sync <= not NMI_n;
|
||||
IRQ_sync <= not IRQ_n;
|
||||
FIRQ_sync <= not FIRQ_n;
|
||||
RES_sync <= not RES_n;
|
||||
HALT_sync <= not HALT_n;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
sync_gen : process(cpu_clk)
|
||||
begin
|
||||
if rising_edge(cpu_clk) then
|
||||
if (RDY_int = '1') then
|
||||
Sync_int <= LIC_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpu_clk <= not E;
|
||||
busmon_clk <= E;
|
||||
|
||||
R_W_n <= 'Z' when TSC = '1' else
|
||||
'1' when memory_rd = '1' else
|
||||
'0' when memory_wr = '1' else
|
||||
R_W_n_int;
|
||||
|
||||
Addr <= (others => 'Z') when TSC = '1' else
|
||||
memory_addr when (memory_rd = '1' or memory_wr = '1') else
|
||||
Addr_int;
|
||||
|
||||
Din <= Data;
|
||||
memory_din <= Data;
|
||||
|
||||
Data <= memory_dout when TSC = '0' and E = '1' and memory_wr = '1' else
|
||||
Dout when TSC = '0' and E = '1' and R_W_n_int = '0' and memory_rd = '0' else
|
||||
(others => 'Z');
|
||||
|
||||
memory_done <= memory_rd or memory_wr;
|
||||
|
||||
BUSY <= '0';
|
||||
LIC <= LIC_int;
|
||||
|
||||
test1 <= Sync_int;
|
||||
test2 <= RDY_int;
|
||||
test3 <= LIC_int;
|
||||
test4 <= clk_count(1);
|
||||
|
||||
end behavioral;
|
||||
5885
src/SYS09/cpu09l.vhd
Normal file
5885
src/SYS09/cpu09l.vhd
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user