mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-06-09 04:29:28 +00:00
20269623ea
Change-Id: I502840a0be0fa58adfc9ddb27c4e2a35a7c2849c
248 lines
7.0 KiB
VHDL
248 lines
7.0 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : MC6808ECpuMon.vhd
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-- /___/ /\ Timestamp : 02/07/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MC6808ECpuMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity MC6809ECpuMon is
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generic (
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UseCPU09Core : boolean := true
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);
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port (
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clock49 : in std_logic;
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--6809 Signals
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E : in std_logic;
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Q : in std_logic;
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RES_n : inout std_logic;
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NMI_n : in std_logic;
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IRQ_n : in std_logic;
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FIRQ_n : in std_logic;
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HALT_n : in std_logic;
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TSC : in std_logic;
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BS : out std_logic;
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BA : out std_logic;
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BUSY : out std_logic;
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R_W_n : out std_logic;
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LIC : out std_logic;
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AVMA : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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nsw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic;
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-- Debugging signals
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test1 : out std_logic;
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test2 : out std_logic;
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test3 : out std_logic;
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test4 : out std_logic
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);
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end MC6809ECpuMon;
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architecture behavioral of MC6809ECpuMon is
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signal cpu_clk : std_logic;
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signal busmon_clk : std_logic;
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signal R_W_n_int : std_logic;
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signal LIC_int : std_logic;
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signal NMI_sync : std_logic;
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signal IRQ_sync : std_logic;
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signal FIRQ_sync : std_logic;
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signal RES_sync : std_logic;
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signal HALT_sync : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Din : std_logic_vector(7 downto 0);
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signal Dout : std_logic_vector(7 downto 0);
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signal Sync_int : std_logic;
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signal Rdy_int : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal memory_addr : std_logic_vector(15 downto 0);
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signal memory_dout : std_logic_vector(7 downto 0);
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signal memory_din : std_logic_vector(7 downto 0);
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signal memory_done : std_logic;
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signal Regs : std_logic_vector(111 downto 0);
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signal Regs1 : std_logic_vector(255 downto 0);
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signal clock7_3728 : std_logic;
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signal clk_count : std_logic_vector(1 downto 0);
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begin
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inst_dcm1 : entity work.DCM1 port map(
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CLKIN_IN => clock49,
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CLK0_OUT => clock7_3728,
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CLK0_OUT1 => open,
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CLK2X_OUT => open
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);
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mon : entity work.BusMonCore
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generic map (
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num_comparators => 4
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)
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port map (
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clock49 => clock49,
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Addr => Addr_int,
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Data => Data,
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Phi2 => busmon_clk,
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Rd_n => not R_W_n_int,
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Wr_n => R_W_n_int,
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RdIO_n => '1',
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => Rdy_int,
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nRSTin => RES_n,
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nRSTout => RES_n,
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CountCycle => Rdy_int,
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trig => trig,
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lcd_rs => open,
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lcd_rw => open,
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lcd_e => open,
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lcd_db => open,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => sw1,
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nsw2 => nsw2,
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led3 => led3,
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led6 => led6,
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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Regs => Regs1,
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RdMemOut=> memory_rd,
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WrMemOut=> memory_wr,
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RdIOOut => open,
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WrIOOut => open,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => memory_done,
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SS_Step => open,
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SS_Single => open
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);
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Regs1(111 downto 0) <= Regs;
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Regs1(255 downto 112) <= (others => '0');
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GenCPU09Core: if UseCPU09Core generate
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inst_cpu09: entity work.cpu09 port map (
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clk => cpu_clk,
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rst => RES_sync,
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vma => AVMA,
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lic_out => LIC_int,
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ifetch => open,
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opfetch => open,
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ba => BA,
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bs => BS,
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addr => Addr_int,
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rw => R_W_n_int,
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data_out => Dout,
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data_in => Din,
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irq => IRQ_sync,
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firq => FIRQ_sync,
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nmi => NMI_sync,
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halt => HALT_sync,
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hold => not RDY_int,
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Regs => Regs
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);
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end generate;
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clk_gen : process(clock7_3728)
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begin
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if rising_edge(clock7_3728) then
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clk_count <= clk_count + 1;
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end if;
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end process;
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irq_gen : process(cpu_clk)
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begin
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if falling_edge(cpu_clk) then
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NMI_sync <= not NMI_n;
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IRQ_sync <= not IRQ_n;
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FIRQ_sync <= not FIRQ_n;
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RES_sync <= not RES_n;
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HALT_sync <= not HALT_n;
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end if;
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end process;
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sync_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (RDY_int = '1') then
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Sync_int <= LIC_int;
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end if;
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end if;
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end process;
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cpu_clk <= not E;
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busmon_clk <= E;
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R_W_n <= 'Z' when TSC = '1' else
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'1' when memory_rd = '1' else
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'0' when memory_wr = '1' else
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R_W_n_int;
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Addr <= (others => 'Z') when TSC = '1' else
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memory_addr when (memory_rd = '1' or memory_wr = '1') else
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Addr_int;
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Din <= Data;
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memory_din <= Data;
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Data <= memory_dout when TSC = '0' and E = '1' and memory_wr = '1' else
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Dout when TSC = '0' and E = '1' and R_W_n_int = '0' and memory_rd = '0' else
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(others => 'Z');
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memory_done <= memory_rd or memory_wr;
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BUSY <= '0';
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LIC <= LIC_int;
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test1 <= Sync_int;
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test2 <= RDY_int;
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test3 <= LIC_int;
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test4 <= clk_count(1);
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end behavioral;
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