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https://github.com/hoglet67/AtomBusMon.git
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Z80: Output NOPs when paused (inc M1)
Change-Id: I100fac021d68662497fbd2d0c7428dcaf9ef98a3
This commit is contained in:
David Banks
parent
ac521aad15
commit
26f0bea110
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@ -104,6 +104,7 @@ type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa,
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signal RFSH_n_int : std_logic;
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signal M1_n_int : std_logic;
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signal WAIT_n_int : std_logic;
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signal WAIT_n_int1 : std_logic;
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signal TState : std_logic_vector(2 downto 0);
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signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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@ -127,6 +128,8 @@ type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa,
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signal io_wr1 : std_logic;
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signal memory_rd1 : std_logic;
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signal memory_wr1 : std_logic;
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signal mon_m1_n : std_logic;
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signal mon_xx_n : std_logic;
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signal mon_mreq_n : std_logic;
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signal mon_iorq_n : std_logic;
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signal mon_rfsh_n : std_logic;
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@ -171,9 +174,6 @@ type state_type is (idle, resume, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa,
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signal avr_TxD_int : std_logic;
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signal clock_49_ctr : std_logic_vector(23 downto 0);
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signal clock_avr_ctr : std_logic_vector(23 downto 0);
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signal rfsh_addr : std_logic_vector(15 downto 0);
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begin
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@ -318,7 +318,7 @@ begin
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skip_opcode_latch : process(CLK_n)
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begin
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if rising_edge(CLK_n) then
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if (M1_n_int = '0' and WAIT_n_int = '1' and TState = "010") then
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if (M1_n_int = '0' and WAIT_n_int1 = '1' and TState = "010") then
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if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
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skipNextOpcode <= '1';
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else
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@ -347,13 +347,15 @@ begin
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watch_gen : process(CLK_n)
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begin
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if falling_edge(CLK_n) then
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Sync <= Sync0;
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Read_n1 <= Read_n0;
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Read_n <= Read_n1;
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Write_n <= Write_n0;
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ReadIO_n1 <= ReadIO_n0;
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ReadIO_n <= ReadIO_n1;
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WriteIO_n <= WriteIO_n0;
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Sync <= Sync0;
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Read_n1 <= Read_n0;
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Read_n <= Read_n1;
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Write_n <= Write_n0;
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ReadIO_n1 <= ReadIO_n0;
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ReadIO_n <= ReadIO_n1;
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WriteIO_n <= WriteIO_n0;
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-- Latch wait seen by T80 on the falling edge, for use on the next rising edge
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WAIT_n_int1 <= WAIT_n_int;
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end if;
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end process;
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@ -390,12 +392,12 @@ begin
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-- TODO: Also need to take account of BUSRQ_n/BUSAK_n
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MREQ_n <= MREQ_n_int when state = idle or state = resume else mon_mreq_n;
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MREQ_n <= MREQ_n_int when state = idle or state = resume else mon_mreq_n and mon_xx_n;
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IORQ_n <= IORQ_n_int when state = idle or state = resume else mon_iorq_n;
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RFSH_n <= RFSH_n_int when state = idle or state = resume else mon_rfsh_n;
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WR_n <= WR_n_int when state = idle or state = resume else mon_wr_n;
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RD_n <= RD_n_int when state = idle or state = resume else mon_rd_n;
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M1_n <= M1_n_int when state = idle or state = resume else '1';
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RD_n <= RD_n_int when state = idle or state = resume else mon_rd_n and mon_xx_n;
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M1_n <= M1_n_int when state = idle or state = resume else mon_m1_n;
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Addr <= Addr_int when state = idle or state = resume else
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x"0000" when state = nop_t1 or state = nop_t2 else
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@ -422,6 +424,8 @@ begin
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io_wr1 <= '0';
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SS_Step_held <= '0';
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mon_rfsh_n <= '1';
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mon_m1_n <= '1';
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mon_xx_n <= '1';
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elsif rising_edge(CLK_n) then
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@ -461,20 +465,31 @@ begin
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-- Idle is when T80 is running
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when idle =>
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if SS_Single = '1' and Sync1 = '1' then
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-- If the T80 is stopped, start genering refresh cycles
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state <= nop_t1;
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-- Load the initial refresh address from I/R in the T80
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rfsh_addr <= Regs(199 downto 192) & Regs(207 downto 200);
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-- Start genering NOP cycles
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if mon_wait_n = '1' then
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state <= nop_t3;
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else
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mon_m1_n <= '0';
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mon_xx_n <= '0';
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state <= nop_t2;
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end if;
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end if;
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-- Refresh cycle
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-- NOP cycle
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when nop_t1 =>
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state <= nop_t2;
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-- Increment the refresh address (7 bits, just like the Z80)
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rfsh_addr(6 downto 0) <= rfsh_addr(6 downto 0) + 1;
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mon_xx_n <= '0';
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when nop_t2 =>
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mon_rfsh_n <= '0';
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state <= nop_t3;
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if mon_wait_n = '1' then
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mon_rfsh_n <= '0';
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state <= nop_t3;
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mon_m1_n <= '1';
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mon_xx_n <= '1';
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end if;
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when nop_t3 =>
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state <= nop_t4;
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when nop_t4 =>
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@ -489,6 +504,7 @@ begin
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state <= resume;
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else
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state <= nop_t1;
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mon_m1_n <= '0';
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end if;
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-- Resume,
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@ -545,8 +561,8 @@ begin
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mon_mreq_n <= '1';
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mon_iorq_n <= '0';
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end if;
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elsif state = nop_t3 then
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-- Refresh cycle
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elsif state = nop_t1 or state = nop_t3 then
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-- M1 cycle
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mon_mreq_n <= '0';
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mon_iorq_n <= '1';
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else
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@ -555,7 +571,7 @@ begin
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mon_iorq_n <= '1';
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end if;
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-- Read strobe
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if state = rd_t1 or state = rd_wa or state = rd_t2 then
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if state = nop_t1 or state = rd_t1 or state = rd_wa or state = rd_t2 then
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mon_rd_n <= '0';
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else
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mon_rd_n <= '1';
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@ -571,35 +587,13 @@ begin
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end if;
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end process;
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RESET_n_int <= RESET_n and sw_interrupt_n and nRST;
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avr_TxD <= avr_Txd_int;
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test1 <= sw_interrupt_n and sw_reset_n;
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process(clock_avr)
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begin
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if rising_edge(clock_avr) then
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clock_avr_ctr <= clock_avr_ctr + 1;
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test2 <= sw_interrupt_n or clock_avr_ctr(23);
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end if;
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end process;
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process(clock49)
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begin
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if rising_edge(clock49) then
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clock_49_ctr <= clock_49_ctr + 1;
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test3 <= sw_reset_n or clock_49_ctr(23);
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end if;
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end process;
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test4 <= not avr_TxD_int;
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--test1 <= TState(0);
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--test2 <= TState(1);
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--test3 <= TState(2);
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--test4 <= CLK_n;
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test1 <= '1';
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test2 <= '1';
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test3 <= '1';
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test4 <= '1';
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end behavioral;
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@ -75,24 +75,44 @@ entity Z80CpuMonALS is
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tcclk : out std_logic;
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-- Optional Debugging signals
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test1 : out std_logic;
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test2 : out std_logic;
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test3 : out std_logic;
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test4 : out std_logic
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test : out std_logic_vector(9 downto 0)
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);
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end Z80CpuMonALS;
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architecture behavioral of Z80CpuMonALS is
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signal BUSAK_n_int : std_logic;
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signal MREQ_n_int : std_logic;
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signal IORQ_n_int : std_logic;
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signal M1_n_int : std_logic;
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signal RD_n_int : std_logic;
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signal WR_n_int : std_logic;
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signal RFSH_n_int : std_logic;
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signal HALT_n_int : std_logic;
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signal BUSAK_n_int : std_logic;
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signal DOE_n : std_logic;
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begin
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BUSAK_n <= BUSAK_n_int;
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MREQ_n <= MREQ_n_int;
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IORQ_n <= IORQ_n_int;
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M1_n <= M1_n_int;
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RD_n <= RD_n_int;
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WR_n <= WR_n_int;
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RFSH_n <= RFSH_n_int;
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HALT_n <= HALT_n_int;
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BUSAK_n <= BUSAK_n_int;
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test(0) <= M1_n_int;
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test(1) <= RD_n_int;
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test(2) <= WR_n_int;
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test(3) <= MREQ_n_int;
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test(4) <= IORQ_n_int;
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test(5) <= WAIT_n;
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test(6) <= RESET_n;
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test(7) <= CLK_n;
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test(8) <= RFSH_n_int;
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test(9) <= INT_n;
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OEC_n <= not BUSAK_n_int;
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OEA1_n <= not BUSAK_n_int;
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@ -123,13 +143,13 @@ begin
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INT_n => INT_n,
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NMI_n => NMI_n,
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BUSRQ_n => BUSRQ_n,
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M1_n => M1_n,
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MREQ_n => MREQ_n,
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IORQ_n => IORQ_n,
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RD_n => RD_n,
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M1_n => M1_n_int,
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MREQ_n => MREQ_n_int,
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IORQ_n => IORQ_n_int,
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RD_n => RD_n_int,
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WR_n => WR_n_int,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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RFSH_n => RFSH_n_int,
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HALT_n => HALT_n_int,
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BUSAK_n => BUSAK_n_int,
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Addr => Addr,
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Data => Data,
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@ -157,10 +177,10 @@ begin
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tcclk => tcclk,
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-- Debugging signals
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test1 => test1,
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test2 => test2,
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test3 => test3,
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test4 => test4
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test1 => open,
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test2 => open,
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test3 => open,
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test4 => open
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);
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end behavioral;
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@ -77,13 +77,19 @@ NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
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NET "trig<0>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
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# 7-segment LED (connect to J5 on FPGA board)
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NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# 7-segment LED (connect to unused pins on adapter)
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NET "tmosi" LOC="P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tdin" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tcclk" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# Test outputs (connect to J5 on FPGA board)
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NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<0>" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<1>" LOC="P47" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<2>" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<3>" LOC="P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<4>" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<5>" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<6>" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<7>" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<8>" LOC="P144" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "test<9>" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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