Updated reset output to avoid the use of a tristate signal in BusMonCore

Change-Id: I3f49317689eb5808a5edb5fe5b10552d01a3db59

src/AtomBusMon.vhd

@@ -64,8 +64,9 @@ end AtomBusMon;
 architecture behavioral of AtomBusMon is
 
 signal clock_avr : std_logic;
-
-signal Rdy_int : std_logic;
+signal Rdy_int   : std_logic;
+signal nRSTin    : std_logic;
+signal nRSTout   : std_logic;
 
 begin
 
@@ -90,8 +91,8 @@ begin
         WrIO_n       => '1',
         Sync         => Sync,
         Rdy          => Rdy_int,
-        nRSTin       => nRST,
-        nRSTout      => nRST,
+        nRSTin       => nRSTin,
+        nRSTout      => nRSTout,
         CountCycle   => Rdy_int,
         Regs         => (others => '0'),
         RdMemOut     => open,
@@ -122,6 +123,10 @@ begin
     );
     Rdy <= Rdy_int;
 
+    -- Tristate buffer driving reset back out
+    nRSTin <= nRST;
+    nRST <= '0' when nRSTout <= '0' else 'Z';
+
 end behavioral;
 
 

src/AtomCpuMon.vhd

@@ -89,7 +89,10 @@ architecture behavioral of AtomCpuMon is
     signal Phi0_d        : std_logic;
     signal cpu_clk       : std_logic;
     signal busmon_clk    : std_logic;
-        
+
+    signal Res_n_in      : std_logic;
+    signal Res_n_out     : std_logic;
+    
 begin
 
     inst_dcm0 : entity work.DCM0 port map(
@@ -118,8 +121,8 @@ begin
         Din          => Din,
         Dout         => Dout,
         SO_n         => SO_n,
-        Res_n_in     => Res_n,
-        Res_n_out    => Res_n,
+        Res_n_in     => Res_n_in,
+        Res_n_out    => Res_n_out,
         Rdy          => Rdy,
         trig         => trig,
         avr_RxD      => avr_RxD,
@@ -133,6 +136,10 @@ begin
         tdin         => tdin,
         tcclk        => tcclk
     );
+
+    -- Tristate buffer driving reset back out
+    Res_n_in <= Res_n;
+    Res_n <= '0' when Res_n_out <= '0' else 'Z';
     
     sync_gen : process(cpu_clk)
     begin

src/BusMonCore.vhd

@@ -306,7 +306,7 @@ begin
            Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
 
     -- Combinatorial set of comparators to decode breakpoint/watch addresses
-    brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n)
+    brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig)
         variable i            : integer;
         variable reg_addr     : std_logic_vector(15 downto 0);
         variable reg_mask     : std_logic_vector(15 downto 0);
@@ -507,12 +507,7 @@ begin
                     Rdy_int <= (not Sync);
                 end if;
                 
-                -- CPU Reset needs to be open collector
-                if (reset = '1') then
-                     nRSTout <= '0';
-                else
-                     nRSTout <= 'Z';
-                end if;
+                nRSTout <= not reset;
                 
                 -- Latch instruction address for the whole cycle
                 if (Sync = '1') then