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https://github.com/hoglet67/AtomBusMon.git
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All: refactor reset logic, add debouncing
Change-Id: Ie7b57ffcb6aa9aedd52e0b633be16775e9eca822
This commit is contained in:
David Banks
parent
ea39bc3ba2
commit
66d109494e
@ -102,7 +102,15 @@ end BusMonCore;
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architecture behavioral of BusMonCore is
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signal cpu_reset_n : std_logic;
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signal nrst_avr : std_logic;
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signal nrst1 : std_logic;
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signal nrst2 : std_logic;
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signal nrst3 : std_logic;
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-- debounce time is 2^17 / 16MHz = 8.192ms
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signal nrst_counter : unsigned(17 downto 0);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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@ -162,6 +170,8 @@ architecture behavioral of BusMonCore is
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signal last_done : std_logic;
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signal inc_addr : std_logic;
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signal reset_counter : std_logic_vector(9 downto 0);
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begin
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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@ -216,7 +226,7 @@ begin
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portdin(3) => '0',
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portdin(4) => '0',
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portdin(5) => '0',
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portdin(6) => sw_interrupt,
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portdin(6) => '0', -- sw_interrupt,
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portdin(7) => fifo_empty_n,
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portdout(0) => muxsel(0),
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@ -408,7 +418,7 @@ begin
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if rising_edge(busmon_clk) then
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if busmon_clken = '1' then
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-- Cycle counter, wraps every 16s at 1MHz
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if (nRSTin = '0') then
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if (cpu_reset_n = '0') then
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cycleCount <= (others => '0');
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elsif (CountCycle = '1') then
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cycleCount <= cycleCount + 1;
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@ -493,8 +503,6 @@ begin
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Rdy_int <= (not Sync);
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end if;
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nRSTout <= not reset;
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-- Latch instruction address for the whole cycle
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if (Sync = '1') then
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addr_inst <= Addr;
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@ -542,4 +550,51 @@ begin
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DataOut <= addr_dout_reg(7 downto 0);
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SS_Single <= single;
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-- Reset Logic
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-- Generate a short (~1ms @ 1MHz) power up reset pulse
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--
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-- This is in case FPGA configuration takes longer than
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-- the length of the host system reset pulse.
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--
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-- Some 6502 cores (particularly the AlanD core) needs
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-- reset to be asserted to start.
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-- Debounce nRSTin using clock_avr as this is always 16MHz
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-- nrst1 is the possibly glitchy input
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-- nrst2 is the filtered output
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process(clock_avr)
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begin
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if rising_edge(clock_avr) then
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-- Syncronise nRSTin
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nrst1 <= nRSTin and (not sw_interrupt);
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-- De-glitch NRST
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if nrst1 = '0' then
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nrst_counter <= to_unsigned(0, nrst_counter'length);
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nrst2 <= '0';
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elsif nrst_counter(nrst_counter'high) = '0' then
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nrst_counter <= nrst_counter + 1;
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else
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nrst2 <= '1';
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end if;
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end if;
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end process;
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process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if cpu_clken = '1' then
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if reset_counter(reset_counter'high) = '0' then
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reset_counter <= reset_counter + 1;
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end if;
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nrst3 <= nrst2;
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cpu_reset_n <= nrst3 and reset_counter(reset_counter'high) and (not reset);
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end if;
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end if;
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end process;
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nRSTout <= cpu_reset_n;
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end behavioral;
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@ -92,12 +92,12 @@ architecture behavioral of MC6809CpuMon is
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signal clock_avr : std_logic;
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signal cpu_clk : std_logic;
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signal cpu_reset_n : std_logic;
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signal busmon_clk : std_logic;
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signal R_W_n_int : std_logic;
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signal NMI_sync : std_logic;
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signal IRQ_sync : std_logic;
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signal FIRQ_sync : std_logic;
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signal nRST_sync : std_logic;
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signal HALT_sync : std_logic;
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signal Addr_int : std_logic_vector(15 downto 0);
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signal Din : std_logic_vector(7 downto 0);
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@ -184,8 +184,8 @@ begin
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => open,
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nRSTin => nRST_sync,
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nRSTout => nRSTout,
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nRSTin => RES_n,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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avr_RxD => avr_RxD,
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@ -244,7 +244,7 @@ begin
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inst_cpu09: entity work.cpu09 port map (
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clk => cpu_clk,
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rst => not nRST_sync,
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rst => not cpu_reset_n,
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vma => AVMA,
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lic_out => LIC_int,
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ifetch => ifetch,
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@ -271,7 +271,6 @@ begin
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NMI_sync <= not NMI_n_masked;
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IRQ_sync <= not IRQ_n_masked;
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FIRQ_sync <= not FIRQ_n_masked;
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nRST_sync <= RES_n and nRSTout;
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HALT_sync <= not HALT_n;
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end if;
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end process;
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@ -85,12 +85,10 @@ architecture behavioral of MOS6502CpuMonCore is
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signal Wr_n_int : std_logic;
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signal Sync_int : std_logic;
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signal Addr_int : std_logic_vector(23 downto 0);
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signal Res_n_out : std_logic;
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signal cpu_addr_us : unsigned (15 downto 0);
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signal cpu_dout_us : unsigned (7 downto 0);
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signal cpu_reset_n : std_logic;
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signal reset_counter : std_logic_vector(9 downto 0);
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signal Regs : std_logic_vector(63 downto 0);
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signal Regs1 : std_logic_vector(255 downto 0);
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@ -135,7 +133,7 @@ begin
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Sync => Sync_int,
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Rdy => open,
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nRSTin => Res_n,
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nRSTout => Res_n_out,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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avr_RxD => avr_RxD,
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@ -196,24 +194,6 @@ begin
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cpu_clken_ss <= '1' when Rdy = '1' and (state = idle) and cpu_clken = '1' else '0';
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-- Generate a short (~1ms @ 1MHz) power up reset pulse
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--
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-- This is in case FPGA configuration takes longer than
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-- the length of the host system reset pulse.
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--
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-- Some 6502 cores (particularly the AlanD core) needs
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-- reset to be asserted to start.
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process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if reset_counter(reset_counter'high) = '0' then
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reset_counter <= reset_counter + 1;
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end if;
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cpu_reset_n <= Res_n and Res_n_out and reset_counter(reset_counter'high);
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end if;
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end process;
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GenT65Core: if UseT65Core generate
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inst_t65: entity work.T65 port map (
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mode => "00",
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@ -94,7 +94,7 @@ type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, r
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signal clock_avr : std_logic;
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signal RESET_n_int : std_logic;
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signal cpu_reset_n : std_logic;
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signal cpu_clk : std_logic;
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signal cpu_clken : std_logic;
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signal busmon_clk : std_logic;
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@ -225,8 +225,8 @@ begin
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WrIO_n => WriteIO_n,
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Sync => Sync,
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Rdy => open,
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nRSTin => RESET_n_int,
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nRSTout => nRST,
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nRSTin => RESET_n,
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nRSTout => cpu_reset_n,
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CountCycle => CountCycle,
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trig => trig,
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avr_RxD => avr_RxD,
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@ -262,7 +262,7 @@ begin
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TS => TState,
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Regs => Regs,
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PdcData => PdcData,
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RESET_n => RESET_n_int,
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RESET_n => cpu_reset_n,
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CLK_n => cpu_clk,
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CEN => cpu_clken,
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WAIT_n => WAIT_n,
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@ -444,9 +444,9 @@ begin
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Din <= Data;
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men_access_machine_rising : process(CLK_n, RESET_n)
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men_access_machine_rising : process(CLK_n, cpu_reset_n)
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begin
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if (RESET_n = '0') then
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if (cpu_reset_n = '0') then
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state <= idle;
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memory_rd1 <= '0';
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memory_wr1 <= '0';
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@ -644,8 +644,6 @@ begin
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mon_busak_n <= mon_busak_n1 or mon_busak_n2;
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RESET_n_int <= RESET_n and (not sw_interrupt) and nRST;
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avr_TxD <= avr_Txd_int;
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test1 <= Sync1;
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