Z80: T80: whitespace
Change-Id: If8617f1a93dd9bb0fc1ff94b2d72924f6db34483
This commit is contained in:
David Banks
parent
8e83d6e21f
commit
670328574b
458
src/T80/T80a.vhd
458
src/T80/T80a.vhd
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@ -80,263 +80,263 @@ use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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entity T80a is
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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IOWait : integer := 1 -- 0 => Single I/O cycle, 1 => Std I/O cycle
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);
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port(
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RESET_n : in std_logic;
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R800_mode : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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D : inout std_logic_vector(7 downto 0)
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);
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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IOWait : integer := 1 -- 0 => Single I/O cycle, 1 => Std I/O cycle
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);
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port(
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RESET_n : in std_logic;
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R800_mode : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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D : inout std_logic_vector(7 downto 0)
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);
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end T80a;
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architecture rtl of T80a is
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signal CEN : std_logic;
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signal Reset_s : std_logic;
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signal IntCycle_n : std_logic;
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signal IORQ : std_logic;
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signal NoRead : std_logic;
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signal Write : std_logic;
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signal MREQ : std_logic;
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signal MReq_Inhibit : std_logic;
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signal Req_Inhibit : std_logic;
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signal RD : std_logic;
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signal MREQ_n_i : std_logic;
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signal MREQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add MREQ control
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signal IORQ_n_i : std_logic;
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signal IORQ_t1 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_int : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ interrupt control
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signal IORQ_int_inhibit : std_logic_vector(2 downto 0);
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signal RD_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal WR_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add WR control
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signal RFSH_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal A_i : std_logic_vector(15 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal Wait_s : std_logic;
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal CEN : std_logic;
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signal Reset_s : std_logic;
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signal IntCycle_n : std_logic;
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signal IORQ : std_logic;
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signal NoRead : std_logic;
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signal Write : std_logic;
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signal MREQ : std_logic;
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signal MReq_Inhibit : std_logic;
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signal Req_Inhibit : std_logic;
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signal RD : std_logic;
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signal MREQ_n_i : std_logic;
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signal MREQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add MREQ control
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signal IORQ_n_i : std_logic;
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signal IORQ_t1 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
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signal IORQ_int : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ interrupt control
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signal IORQ_int_inhibit : std_logic_vector(2 downto 0);
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signal RD_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal WR_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add WR control
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signal RFSH_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal A_i : std_logic_vector(15 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal Wait_s : std_logic;
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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begin
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CEN <= '1';
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CEN <= '1';
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BUSAK_n <= BUSAK_n_i; -- 30/10/19 Charlie Ingley - IORQ/RD/WR changes
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MREQ_rw <= MREQ and (Req_Inhibit or MReq_Inhibit); -- added MREQ timing control
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MREQ_n_i <= not MREQ_rw; -- changed MREQ generation
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IORQ_rw <= IORQ and not (IORQ_t1 or IORQ_t2); -- added IORQ generation timing control
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IORQ_n_i <= not ((IORQ_int and not IORQ_int_inhibit(2)) or IORQ_rw); -- changed IORQ generation
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RD_n_i <= not (RD and (MREQ_rw or IORQ_rw)); -- changed RD/IORQ generation
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WR_n_i <= not (Write and ((WR_t2 and MREQ_rw) or IORQ_rw)); -- added WR/IORQ timing control
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BUSAK_n <= BUSAK_n_i; -- 30/10/19 Charlie Ingley - IORQ/RD/WR changes
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MREQ_rw <= MREQ and (Req_Inhibit or MReq_Inhibit); -- added MREQ timing control
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MREQ_n_i <= not MREQ_rw; -- changed MREQ generation
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IORQ_rw <= IORQ and not (IORQ_t1 or IORQ_t2); -- added IORQ generation timing control
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IORQ_n_i <= not ((IORQ_int and not IORQ_int_inhibit(2)) or IORQ_rw); -- changed IORQ generation
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RD_n_i <= not (RD and (MREQ_rw or IORQ_rw)); -- changed RD/IORQ generation
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WR_n_i <= not (Write and ((WR_t2 and MREQ_rw) or IORQ_rw)); -- added WR/IORQ timing control
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MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
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IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
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RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
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RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
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MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
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IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
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RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
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RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
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process (RESET_n, CLK_n)
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begin
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if RESET_n = '0' then
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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Reset_s <= '1';
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end if;
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end process;
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process (RESET_n, CLK_n)
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begin
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if RESET_n = '0' then
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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Reset_s <= '1';
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end if;
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end process;
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u0 : T80
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generic map(
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Mode => Mode,
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IOWait => IOWait)
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port map(
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R800_mode => R800_mode,
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CEN => CEN,
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M1_n => M1_n,
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IORQ => IORQ,
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NoRead => NoRead,
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Write => Write,
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RFSH_n => RFSH_n_i,
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HALT_n => HALT_n,
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WAIT_n => Wait_s,
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INT_n => INT_n,
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NMI_n => NMI_n,
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RESET_n => Reset_s,
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BUSRQ_n => BUSRQ_n,
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BUSAK_n => BUSAK_n_i,
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CLK_n => CLK_n,
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A => A_i,
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DInst => D,
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DI => DI_Reg,
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DO => DO,
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MC => MCycle,
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TS => TState,
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IntCycle_n => IntCycle_n);
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u0 : T80
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generic map(
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Mode => Mode,
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IOWait => IOWait)
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port map(
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R800_mode => R800_mode,
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CEN => CEN,
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M1_n => M1_n,
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IORQ => IORQ,
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NoRead => NoRead,
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Write => Write,
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RFSH_n => RFSH_n_i,
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HALT_n => HALT_n,
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WAIT_n => Wait_s,
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INT_n => INT_n,
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NMI_n => NMI_n,
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RESET_n => Reset_s,
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BUSRQ_n => BUSRQ_n,
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BUSAK_n => BUSAK_n_i,
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CLK_n => CLK_n,
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A => A_i,
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DInst => D,
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DI => DI_Reg,
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DO => DO,
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MC => MCycle,
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TS => TState,
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IntCycle_n => IntCycle_n);
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process (CLK_n)
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begin
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if CLK_n'event and CLK_n = '0' then
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Wait_s <= WAIT_n;
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if TState = "011" and BUSAK_n_i = '1' then
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DI_Reg <= to_x01(D);
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end if;
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end if;
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end process;
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process (CLK_n)
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begin
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if CLK_n'event and CLK_n = '0' then
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Wait_s <= WAIT_n;
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if TState = "011" and BUSAK_n_i = '1' then
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DI_Reg <= to_x01(D);
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end if;
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end if;
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end process;
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-- 30/10/19 Charlie Ingley - Generate WR_t2 to correct MREQ/WR timing
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process (Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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WR_t2 <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle /= "001" then
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if TState = "010" then -- WR starts on falling edge of T2 for MREQ
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WR_t2 <= Write;
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end if;
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end if;
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if TState = "011" then -- end WR
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process (Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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WR_t2 <= '0';
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end if;
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end if;
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end process;
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle /= "001" then
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if TState = "010" then -- WR starts on falling edge of T2 for MREQ
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WR_t2 <= Write;
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end if;
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end if;
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if TState = "011" then -- end WR
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WR_t2 <= '0';
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end if;
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end if;
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end process;
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-- Generate Req_Inhibit
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process (Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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Req_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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elsif CLK_n'event and CLK_n = '1' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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Req_Inhibit <= '0';
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else
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Req_Inhibit <= '1';
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end if;
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end if;
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end process;
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process (Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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Req_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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elsif CLK_n'event and CLK_n = '1' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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Req_Inhibit <= '0';
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else
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Req_Inhibit <= '1';
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end if;
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end if;
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end process;
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-- Generate MReq_Inhibit
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process (Reset_s, CLK_n)
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begin
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if Reset_s = '0' then
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MReq_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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MReq_Inhibit <= '0';
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else
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MReq_Inhibit <= '1';
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end if;
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end if;
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end process;
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process (Reset_s, CLK_n)
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begin
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if Reset_s = '0' then
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MReq_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
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MReq_Inhibit <= '0';
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else
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MReq_Inhibit <= '1';
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end if;
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end if;
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end process;
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-- Generate RD for MREQ
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process(Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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RD <= '0';
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MREQ <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle = "001" then
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if TState = "001" then
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RD <= IntCycle_n;
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MREQ <= IntCycle_n;
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end if;
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if TState = "011" then
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RD <= '0';
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MREQ <= '1';
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end if;
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if TState = "100" then
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MREQ <= '0';
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end if;
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else
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if TState = "001" and NoRead = '0' then
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RD <= not Write;
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MREQ <= not IORQ;
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end if;
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if TState = "011" then
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RD <= '0';
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MREQ <= '0';
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end if;
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end if;
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end if;
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end process;
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-- 30/10/19 Charlie Ingley - Generate IORQ_int for IORQ interrupt timing control
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process(Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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IORQ_int <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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if MCycle = "001" then
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if TState = "001" then
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IORQ_int <= not IntCycle_n;
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end if;
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if TState = "010" then
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IORQ_int <= '0';
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end if;
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end if;
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end if;
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end process;
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process(Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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IORQ_int_inhibit <= "111";
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elsif CLK_n'event and CLK_n = '0' then
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if IntCycle_n = '0' then
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process(Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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RD <= '0';
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MREQ <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle = "001" then
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IORQ_int_inhibit <= IORQ_int_inhibit(1 downto 0) & '0';
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if TState = "001" then
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RD <= IntCycle_n;
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MREQ <= IntCycle_n;
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end if;
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if TState = "011" then
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RD <= '0';
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MREQ <= '1';
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end if;
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if TState = "100" then
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MREQ <= '0';
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end if;
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else
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if TState = "001" and NoRead = '0' then
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RD <= not Write;
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MREQ <= not IORQ;
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end if;
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if TState = "011" then
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RD <= '0';
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MREQ <= '0';
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end if;
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end if;
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if MCycle = "010" then
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IORQ_int_inhibit <= "111";
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end if;
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end process;
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-- 30/10/19 Charlie Ingley - Generate IORQ_int for IORQ interrupt timing control
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process(Reset_s,CLK_n)
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begin
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if Reset_s = '0' then
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IORQ_int <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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if MCycle = "001" then
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if TState = "001" then
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IORQ_int <= not IntCycle_n;
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end if;
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if TState = "010" then
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IORQ_int <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
IORQ_int_inhibit <= "111";
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if IntCycle_n = '0' then
|
||||
if MCycle = "001" then
|
||||
IORQ_int_inhibit <= IORQ_int_inhibit(1 downto 0) & '0';
|
||||
end if;
|
||||
if MCycle = "010" then
|
||||
IORQ_int_inhibit <= "111";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t1 for IORQ timing control
|
||||
process(Reset_s, CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
IORQ_t1 <= '1';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if TState = "001" then
|
||||
IORQ_t1 <= not IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
process(Reset_s, CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
IORQ_t1 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if TState = "001" then
|
||||
IORQ_t1 <= not IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
IORQ_t1 <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- 30/10/19 Charlie Ingley - Generate IORQ_t2 for IORQ timing control
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
IORQ_t2 <= '1';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
IORQ_t2 <= IORQ_t1;
|
||||
end if;
|
||||
end process;
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
IORQ_t2 <= '1';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
IORQ_t2 <= IORQ_t1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
|
|
|
|||
Loading…
Reference in New Issue