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Kicad v2: more tidying; add logo

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Change-Id: I0f30f7ad6e5b9fd4cd53931bdb14ebcec43bfbde
This commit is contained in:
David Banks 2019-09-13 12:26:50 +01:00
parent 1c7d4a67d7
commit 753b10e4cf
1 changed files with 109 additions and 91 deletions
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200
kicad/6502/v2/6502_adapter.kicad_pcb
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@ -2,8 +2,8 @@
(general
(thickness 1.6)
(drawings 35)
(tracks 726)
(drawings 45)
(tracks 732)
(zones 0)
(modules 46)
(nets 132)
@ -46,7 +46,7 @@
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(trace_min 0.25)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
@ -1993,7 +1993,7 @@
(tags "capacitor handsolder")
(path /597624D7)
(attr smd)
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)
(fp_text value 100nF (at 0 1.65 90) (layer F.Fab)
@ -2508,7 +2508,7 @@
)
)
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(at 184.785 109.22 180)
(descr "24-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
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