mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2026-01-23 03:16:20 +00:00
Altera: Initial 6502 and 65C02 build
Change-Id: I8aa918bfce1b58106a73631907af33841d519d06
This commit is contained in:
David Banks
222
src/MOS6502CpuMonEP4CE6E22C.vhd
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222
src/MOS6502CpuMonEP4CE6E22C.vhd
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@@ -0,0 +1,222 @@
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--------------------------------------------------------------------------------
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||||
-- Copyright (c) 2025 David Banks
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||||
--
|
||||
--------------------------------------------------------------------------------
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||||
-- ____ ____
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-- / /\/ /
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||||
-- /___/ \ /
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||||
-- \ \ \/
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-- \ \
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-- / / Filename : MOS6502CpuMonEP4CE6E22C.vhd
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-- /___/ /\ Timestamp : 20/09/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: MOS6502CpuMonEP4CE6E22C
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--Device: XC6SLX9
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--
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--
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-- This is a small wrapper around MOS6502CpuMon that add the following signals:
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-- OEAH_n
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-- OEAL_n
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-- OED_n
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-- DIRD
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-- BE
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-- ML_n
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-- VP_n
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-- (these are not fully implemented yet)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity MOS6502CpuMonEP4CE6E22C is
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false;
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num_comparators : integer := 8;
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avr_prog_mem_size : integer := 8 * 1024
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);
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port (
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clock : in std_logic;
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-- 6502 Signals
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PhiIn : in std_logic;
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Phi1Out : out std_logic;
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Phi2Out : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic_vector(1 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : in std_logic;
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Rdy : in std_logic;
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-- 65C02 Signals
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BE : in std_logic;
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ML_n : out std_logic;
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VP_n : out std_logic;
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-- Level Shifter Controls
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OERW_n : out std_logic;
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OEAH_n : out std_logic;
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OEAL_n : out std_logic;
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OED_n : out std_logic;
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DIRD : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- ID/mode inputs
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mode : in std_logic;
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id : in std_logic_vector(3 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Serial Flash
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flash_cs_n : out std_logic;
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flash_clk : out std_logic;
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flash_di : out std_logic;
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flash_do : in std_logic;
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-- Switches
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sw : in std_logic_vector(5 downto 1);
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-- LEDs
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led : out std_logic_vector(5 downto 1)
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);
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end MOS6502CpuMonEP4CE6E22C;
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architecture behavioral of MOS6502CpuMonEP4CE6E22C is
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signal R_W_n_int : std_logic;
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signal sw_reset_cpu : std_logic;
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signal sw_reset_avr : std_logic;
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signal led_bkpt : std_logic;
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signal led_trig0 : std_logic;
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signal led_trig1 : std_logic;
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signal PhiIn1 : std_logic;
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signal PhiIn2 : std_logic;
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signal PhiIn3 : std_logic;
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signal PhiIn4 : std_logic;
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-- 50MHz clock, toggle every 25,000,000 =
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signal blinky_count : unsigned(24 downto 0) := (others => '0');
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signal led_blinky : std_logic := '0';
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begin
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sw_reset_cpu <= not sw(1);
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sw_reset_avr <= not sw(2);
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led(1) <= sw(1) and sw(2);
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led(2) <= not led_bkpt;
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led(3) <= not led_trig0;
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led(4) <= not led_trig1;
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led(5) <= led_blinky;
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-- 1Hz Blinky LED
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process(clock)
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begin
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if rising_edge(clock) then
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if blinky_count = to_unsigned(24999999, blinky_count'length) then
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blinky_count <= (others => '0');
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led_blinky <= not led_blinky;
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else
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blinky_count <= blinky_count + 1;
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end if;
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end if;
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end process;
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wrapper : entity work.MOS6502CpuMon
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generic map (
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UseT65Core => UseT65Core,
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UseAlanDCore => UseAlanDCore,
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ClkMult => 12,
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ClkDiv => 25,
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ClkPer => 20.000,
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num_comparators => num_comparators,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock => clock,
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-- 6502 Signals
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Phi0 => PhiIn,
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Phi1 => Phi1Out,
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Phi2 => Phi2Out,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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Sync => Sync,
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Addr => Addr,
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R_W_n => R_W_n_int,
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Data => Data,
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SO_n => SO_n,
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Res_n => Res_n,
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Rdy => Rdy,
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|
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-- External trigger inputs
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trig => trig,
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-- Jumpers
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fakeTube_n => '1',
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-- Serial Console
|
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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||||
|
||||
-- Switches
|
||||
sw_reset_cpu => sw_reset_cpu,
|
||||
sw_reset_avr => sw_reset_avr,
|
||||
|
||||
-- LEDs
|
||||
led_bkpt => led_bkpt,
|
||||
led_trig0 => led_trig0,
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||||
led_trig1 => led_trig1,
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||||
|
||||
-- OHO_DY1 LED display
|
||||
tmosi => open,
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||||
tdin => open,
|
||||
tcclk => open,
|
||||
|
||||
-- Test signals
|
||||
test => open
|
||||
);
|
||||
|
||||
-- 6502 Outputs
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||||
R_W_n <= R_W_n_int & R_W_n_int;
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||||
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-- 65C02 Outputs
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ML_n <= '1';
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VP_n <= '1';
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process(clock)
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begin
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||||
if rising_edge(clock) then
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PhiIn1 <= PhiIn;
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PhiIn2 <= PhiIn1;
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||||
PhiIn3 <= PhiIn2;
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||||
PhiIn4 <= PhiIn3;
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||||
end if;
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||||
|
||||
end process;
|
||||
|
||||
-- Level Shifter Controls
|
||||
OERW_n <= '0'; -- not (BE);
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OEAH_n <= '0'; -- not (BE);
|
||||
OEAL_n <= '0'; -- not (BE);
|
||||
OED_n <= not (BE and PhiIn and PhiIn4); -- TODO: might need to use a slightly delayed version of Phi2 here
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||||
DIRD <= R_W_n_int;
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||||
|
||||
-- Unused serial flash:
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||||
flash_cs_n <= '1';
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||||
flash_clk <= '1';
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||||
flash_di <= '1';
|
||||
|
||||
end behavioral;
|
||||
@@ -33,7 +33,7 @@ output_files/$(TARGET).sof: $(PROG).mif
|
||||
|
||||
$(PROG).mif: $(PROG).bin
|
||||
echo "WIDTH=16;" > $(PROG).mif
|
||||
echo "DEPTH=9216;" >> $(PROG).mif
|
||||
echo "DEPTH=$(XPM_SIZE);" >> $(PROG).mif
|
||||
echo "ADDRESS_RADIX=UNS;" >> $(PROG).mif
|
||||
echo "DATA_RADIX=HEX;" >> $(PROG).mif
|
||||
echo "CONTENT BEGIN" >> $(PROG).mif
|
||||
|
||||
22
target/ep4ce6e22c/ice6502/Makefile
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22
target/ep4ce6e22c/ice6502/Makefile
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@@ -0,0 +1,22 @@
|
||||
# The root directory of the project
|
||||
ROOT = ../../..
|
||||
|
||||
# The common directory for makefile includes, etc.
|
||||
COMMON = ../../common
|
||||
|
||||
# The target bitstream file to be generated including the monitor program
|
||||
TARGET = ice6502
|
||||
|
||||
# Frequuency that the AVR runs at
|
||||
F_CPU = 24000000
|
||||
|
||||
# Default Baud Rate of serial interface
|
||||
# Note: F_CPU / 16 / BAUD need to be close to an integer
|
||||
BAUD = 115200
|
||||
|
||||
# Size of the XPM Memory in words
|
||||
XPM_SIZE = 8192
|
||||
|
||||
# Common include files
|
||||
include $(COMMON)/Makefile_$(TARGET).inc
|
||||
include $(COMMON)/Makefile_Altera.inc
|
||||
31
target/ep4ce6e22c/ice6502/ice6502.qpf
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31
target/ep4ce6e22c/ice6502/ice6502.qpf
Normal file
@@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
|
||||
# Date created = 14:44:08 November 25, 2025
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "20.1"
|
||||
DATE = "14:44:08 November 25, 2025"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "ice6502"
|
||||
252
target/ep4ce6e22c/ice6502/ice6502.qsf
Normal file
252
target/ep4ce6e22c/ice6502/ice6502.qsf
Normal file
@@ -0,0 +1,252 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
|
||||
# Date created = 14:44:09 November 25, 2025
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# MOS6502CpuMonCycloneIV_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE6E22C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY MOS6502CpuMonEP4CE6E22C
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:44:09 NOVEMBER 25, 2025"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AlanD/R65Cx2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/avr_adr_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/AVRuCPackage.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/std_library.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/SynthCtrlPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/alu_avr.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/AVR_Core_CompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/avr_core.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/bit_processor.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_adr_dec.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_reg_file.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/pm_fetch_dec.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/reg_file.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemRdMux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XDM_Generic.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XPM_Altera.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/portx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerDFF.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerLatch.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/Timer_Counter.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_bit.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_mod.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR8.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR_uC_CompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/external_mux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ExtIRQ_Controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/RAMDataReg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMonEP4CE6E22C.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMonCore.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMon.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65.vhd
|
||||
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
|
||||
# Top Level VHDL Parameters
|
||||
set_parameter -name UseAlanDCore false
|
||||
set_parameter -name UseT65Core true
|
||||
|
||||
# On-board peripherals
|
||||
set_location_assignment PIN_24 -to clock
|
||||
set_location_assignment PIN_10 -to avr_TxD
|
||||
set_location_assignment PIN_23 -to avr_RxD
|
||||
set_location_assignment PIN_114 -to sw[1]
|
||||
set_location_assignment PIN_89 -to sw[2]
|
||||
set_location_assignment PIN_88 -to sw[3]
|
||||
set_location_assignment PIN_80 -to sw[4]
|
||||
set_location_assignment PIN_73 -to sw[5]
|
||||
set_location_assignment PIN_1 -to led[1]
|
||||
set_location_assignment PIN_2 -to led[2]
|
||||
set_location_assignment PIN_3 -to led[3]
|
||||
set_location_assignment PIN_7 -to led[4]
|
||||
set_location_assignment PIN_11 -to led[5]
|
||||
set_location_assignment PIN_87 -to flash_cs_n
|
||||
set_location_assignment PIN_75 -to flash_clk
|
||||
set_location_assignment PIN_74 -to flash_di
|
||||
set_location_assignment PIN_84 -to flash_do
|
||||
|
||||
# DIP Pins 1..20 (VSS=1;VCC=8) mapped to Connector A
|
||||
set_location_assignment PIN_144 -to VP_n
|
||||
set_location_assignment PIN_143 -to Rdy
|
||||
set_location_assignment PIN_142 -to Phi1Out
|
||||
set_location_assignment PIN_141 -to IRQ_n
|
||||
set_location_assignment PIN_138 -to ML_n
|
||||
set_location_assignment PIN_137 -to NMI_n
|
||||
set_location_assignment PIN_136 -to SYNC
|
||||
set_location_assignment PIN_135 -to Addr[0]
|
||||
set_location_assignment PIN_133 -to Addr[1]
|
||||
set_location_assignment PIN_132 -to Addr[2]
|
||||
set_location_assignment PIN_129 -to Addr[3]
|
||||
set_location_assignment PIN_128 -to Addr[4]
|
||||
set_location_assignment PIN_127 -to Addr[5]
|
||||
set_location_assignment PIN_126 -to Addr[6]
|
||||
set_location_assignment PIN_125 -to Addr[7]
|
||||
set_location_assignment PIN_124 -to Addr[8]
|
||||
set_location_assignment PIN_121 -to Addr[9]
|
||||
set_location_assignment PIN_120 -to Addr[10]
|
||||
set_location_assignment PIN_119 -to Addr[11]
|
||||
|
||||
|
||||
# DIP Pins 40..21 (GND=29) mapped to connector B
|
||||
set_location_assignment PIN_38 -to Res_n
|
||||
set_location_assignment PIN_39 -to Phi2Out
|
||||
set_location_assignment PIN_42 -to SO_n
|
||||
set_location_assignment PIN_43 -to PhiIn
|
||||
set_location_assignment PIN_44 -to BE
|
||||
set_location_assignment PIN_46 -to R_W_n[1]
|
||||
set_location_assignment PIN_49 -to R_W_n[0]
|
||||
set_location_assignment PIN_50 -to Data[0]
|
||||
set_location_assignment PIN_51 -to Data[1]
|
||||
set_location_assignment PIN_52 -to Data[2]
|
||||
set_location_assignment PIN_53 -to Data[3]
|
||||
set_location_assignment PIN_54 -to Data[4]
|
||||
set_location_assignment PIN_55 -to Data[5]
|
||||
set_location_assignment PIN_58 -to Data[6]
|
||||
set_location_assignment PIN_59 -to Data[7]
|
||||
set_location_assignment PIN_60 -to Addr[15]
|
||||
set_location_assignment PIN_64 -to Addr[14]
|
||||
set_location_assignment PIN_65 -to Addr[13]
|
||||
set_location_assignment PIN_66 -to Addr[12]
|
||||
|
||||
# Level shifter controls mapped to spare pins on Connectors A and B
|
||||
set_location_assignment PIN_113 -to OEAL_n
|
||||
set_location_assignment PIN_112 -to OEAH_n
|
||||
set_location_assignment PIN_111 -to OED_n
|
||||
set_location_assignment PIN_110 -to DIRD
|
||||
set_location_assignment PIN_72 -to OERW_n
|
||||
|
||||
# Misc mapped to Connector C
|
||||
set_location_assignment PIN_106 -to trig[1]
|
||||
set_location_assignment PIN_104 -to trig[0]
|
||||
set_location_assignment PIN_86 -to id[3]
|
||||
set_location_assignment PIN_83 -to id[2]
|
||||
set_location_assignment PIN_28 -to id[1]
|
||||
set_location_assignment PIN_31 -to id[0]
|
||||
set_location_assignment PIN_33 -to mode
|
||||
|
||||
# Output drive strengths
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Phi1Out
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Phi2Out
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Sync
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to R_W_n[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to R_W_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ML_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VP_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OERW_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEAH_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEAL_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OED_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DIRD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to avr_TxD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_cs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_clk
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_di
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[7]
|
||||
44
target/ep4ce6e22c/ice6502/ice6502.sdc
Normal file
44
target/ep4ce6e22c/ice6502/ice6502.sdc
Normal file
@@ -0,0 +1,44 @@
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
# External 50MHz clock input from on-board crystal
|
||||
create_clock -period "50 MHz" -name clock_50 [get_ports clock]
|
||||
|
||||
# 6502 PhiIn clock input
|
||||
create_clock -period "16 MHz" -name clock_phi [get_ports PhiIn]
|
||||
|
||||
# 6502 PhiIn clock input delayed internally
|
||||
create_clock -period "16 MHz" -name clock_phi_a {MOS6502CpuMon:wrapper|Phi0_a}
|
||||
|
||||
# 6502 PhiIn clock input delayed internally
|
||||
create_clock -period "16 MHz" -name clock_phi_d {MOS6502CpuMon:wrapper|Phi0_d}
|
||||
|
||||
# Trig(0) clock input
|
||||
create_clock -period "16 MHz" -name clock_trig0 [get_ports TRIG[0]]
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
# Doing this manually above so we can name the clock
|
||||
# derive_pll_clocks
|
||||
|
||||
#create_generated_clock -source {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]}
|
||||
|
||||
create_generated_clock -source [get_ports clock] -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]}
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
derive_clock_uncertainty
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group {clock_avr} -group {clock_phi_d}
|
||||
set_clock_groups -asynchronous -group {clock_phi_d} -group {clock_avr}
|
||||
|
||||
set_clock_groups -asynchronous -group {clock_avr} -group {clock_trig0}
|
||||
set_clock_groups -asynchronous -group {clock_trig0} -group {clock_avr}
|
||||
22
target/ep4ce6e22c/ice65c02/Makefile
Normal file
22
target/ep4ce6e22c/ice65c02/Makefile
Normal file
@@ -0,0 +1,22 @@
|
||||
# The root directory of the project
|
||||
ROOT = ../../..
|
||||
|
||||
# The common directory for makefile includes, etc.
|
||||
COMMON = ../../common
|
||||
|
||||
# The target bitstream file to be generated including the monitor program
|
||||
TARGET = ice65c02
|
||||
|
||||
# Frequuency that the AVR runs at
|
||||
F_CPU = 24000000
|
||||
|
||||
# Default Baud Rate of serial interface
|
||||
# Note: F_CPU / 16 / BAUD need to be close to an integer
|
||||
BAUD = 115200
|
||||
|
||||
# Size of the XPM Memory in words
|
||||
XPM_SIZE = 8192
|
||||
|
||||
# Common include files
|
||||
include $(COMMON)/Makefile_$(TARGET).inc
|
||||
include $(COMMON)/Makefile_Altera.inc
|
||||
32
target/ep4ce6e22c/ice65c02/ice65c02.qpf
Normal file
32
target/ep4ce6e22c/ice65c02/ice65c02.qpf
Normal file
@@ -0,0 +1,32 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2025 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
# the Altera IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Altera and sold by Altera or its authorized distributors. Please
|
||||
# refer to the Altera Software License Subscription Agreements
|
||||
# on the Quartus Prime software download page.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
# Date created = 15:25:25 November 29, 2025
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "25.1"
|
||||
DATE = "15:25:25 November 29, 2025"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "ice65c02"
|
||||
PROJECT_REVISION = "ice6502"
|
||||
252
target/ep4ce6e22c/ice65c02/ice65c02.qsf
Normal file
252
target/ep4ce6e22c/ice65c02/ice65c02.qsf
Normal file
@@ -0,0 +1,252 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
|
||||
# Date created = 14:44:09 November 25, 2025
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# MOS6502CpuMonCycloneIV_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE6E22C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY MOS6502CpuMonEP4CE6E22C
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:44:09 NOVEMBER 25, 2025"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
|
||||
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AlanD/R65Cx2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/avr_adr_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/AVRuCPackage.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/spi_mod_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/std_library.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/CommonPacks/SynthCtrlPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/alu_avr.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/AVR_Core_CompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/avr_core.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/bit_processor.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_adr_dec.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/io_reg_file.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/pm_fetch_dec.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Core/reg_file.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/MemRdMux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XDM_Generic.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Memory/XPM_Altera.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/portx.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerCompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerDFF.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/SynchronizerLatch.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/Timer_Counter.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/Peripheral/uart.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_bit.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/resync/rsnc_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_mod.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/spi_mod/spi_slv_sel.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR8.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/AVR_uC_CompPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/external_mux.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ExtIRQ_Controller.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/RAMDataReg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/AVR8/uC/ResetGenerator.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/altera/DCM0.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/altera/WatchEvents_CycloneIV.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/BusMonCore.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMonEP4CE6E22C.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMonCore.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/MOS6502CpuMon.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/Oho_Dy1.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/oho_dy1/OhoPack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../src/T6502/T65.vhd
|
||||
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
|
||||
# Top Level VHDL Parameters
|
||||
set_parameter -name UseAlanDCore true
|
||||
set_parameter -name UseT65Core false
|
||||
|
||||
# On-board peripherals
|
||||
set_location_assignment PIN_24 -to clock
|
||||
set_location_assignment PIN_10 -to avr_TxD
|
||||
set_location_assignment PIN_23 -to avr_RxD
|
||||
set_location_assignment PIN_114 -to sw[1]
|
||||
set_location_assignment PIN_89 -to sw[2]
|
||||
set_location_assignment PIN_88 -to sw[3]
|
||||
set_location_assignment PIN_80 -to sw[4]
|
||||
set_location_assignment PIN_73 -to sw[5]
|
||||
set_location_assignment PIN_1 -to led[1]
|
||||
set_location_assignment PIN_2 -to led[2]
|
||||
set_location_assignment PIN_3 -to led[3]
|
||||
set_location_assignment PIN_7 -to led[4]
|
||||
set_location_assignment PIN_11 -to led[5]
|
||||
set_location_assignment PIN_87 -to flash_cs_n
|
||||
set_location_assignment PIN_75 -to flash_clk
|
||||
set_location_assignment PIN_74 -to flash_di
|
||||
set_location_assignment PIN_84 -to flash_do
|
||||
|
||||
# DIP Pins 1..20 (VSS=1;VCC=8) mapped to Connector A
|
||||
set_location_assignment PIN_144 -to VP_n
|
||||
set_location_assignment PIN_143 -to Rdy
|
||||
set_location_assignment PIN_142 -to Phi1Out
|
||||
set_location_assignment PIN_141 -to IRQ_n
|
||||
set_location_assignment PIN_138 -to ML_n
|
||||
set_location_assignment PIN_137 -to NMI_n
|
||||
set_location_assignment PIN_136 -to SYNC
|
||||
set_location_assignment PIN_135 -to Addr[0]
|
||||
set_location_assignment PIN_133 -to Addr[1]
|
||||
set_location_assignment PIN_132 -to Addr[2]
|
||||
set_location_assignment PIN_129 -to Addr[3]
|
||||
set_location_assignment PIN_128 -to Addr[4]
|
||||
set_location_assignment PIN_127 -to Addr[5]
|
||||
set_location_assignment PIN_126 -to Addr[6]
|
||||
set_location_assignment PIN_125 -to Addr[7]
|
||||
set_location_assignment PIN_124 -to Addr[8]
|
||||
set_location_assignment PIN_121 -to Addr[9]
|
||||
set_location_assignment PIN_120 -to Addr[10]
|
||||
set_location_assignment PIN_119 -to Addr[11]
|
||||
|
||||
|
||||
# DIP Pins 40..21 (GND=29) mapped to connector B
|
||||
set_location_assignment PIN_38 -to Res_n
|
||||
set_location_assignment PIN_39 -to Phi2Out
|
||||
set_location_assignment PIN_42 -to SO_n
|
||||
set_location_assignment PIN_43 -to PhiIn
|
||||
set_location_assignment PIN_44 -to BE
|
||||
set_location_assignment PIN_46 -to R_W_n[1]
|
||||
set_location_assignment PIN_49 -to R_W_n[0]
|
||||
set_location_assignment PIN_50 -to Data[0]
|
||||
set_location_assignment PIN_51 -to Data[1]
|
||||
set_location_assignment PIN_52 -to Data[2]
|
||||
set_location_assignment PIN_53 -to Data[3]
|
||||
set_location_assignment PIN_54 -to Data[4]
|
||||
set_location_assignment PIN_55 -to Data[5]
|
||||
set_location_assignment PIN_58 -to Data[6]
|
||||
set_location_assignment PIN_59 -to Data[7]
|
||||
set_location_assignment PIN_60 -to Addr[15]
|
||||
set_location_assignment PIN_64 -to Addr[14]
|
||||
set_location_assignment PIN_65 -to Addr[13]
|
||||
set_location_assignment PIN_66 -to Addr[12]
|
||||
|
||||
# Level shifter controls mapped to spare pins on Connectors A and B
|
||||
set_location_assignment PIN_113 -to OEAL_n
|
||||
set_location_assignment PIN_112 -to OEAH_n
|
||||
set_location_assignment PIN_111 -to OED_n
|
||||
set_location_assignment PIN_110 -to DIRD
|
||||
set_location_assignment PIN_72 -to OERW_n
|
||||
|
||||
# Misc mapped to Connector C
|
||||
set_location_assignment PIN_106 -to trig[1]
|
||||
set_location_assignment PIN_104 -to trig[0]
|
||||
set_location_assignment PIN_86 -to id[3]
|
||||
set_location_assignment PIN_83 -to id[2]
|
||||
set_location_assignment PIN_28 -to id[1]
|
||||
set_location_assignment PIN_31 -to id[0]
|
||||
set_location_assignment PIN_33 -to mode
|
||||
|
||||
# Output drive strengths
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Phi1Out
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Phi2Out
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Sync
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Addr[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to R_W_n[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to R_W_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to ML_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VP_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OERW_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEAH_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OEAL_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to OED_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to DIRD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to avr_TxD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_cs_n
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_clk
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to flash_di
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to led[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to Data[7]
|
||||
44
target/ep4ce6e22c/ice65c02/ice65c02.sdc
Normal file
44
target/ep4ce6e22c/ice65c02/ice65c02.sdc
Normal file
@@ -0,0 +1,44 @@
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
# External 50MHz clock input from on-board crystal
|
||||
create_clock -period "50 MHz" -name clock_50 [get_ports clock]
|
||||
|
||||
# 6502 PhiIn clock input
|
||||
create_clock -period "16 MHz" -name clock_phi [get_ports PhiIn]
|
||||
|
||||
# 6502 PhiIn clock input delayed internally
|
||||
create_clock -period "16 MHz" -name clock_phi_a {MOS6502CpuMon:wrapper|Phi0_a}
|
||||
|
||||
# 6502 PhiIn clock input delayed internally
|
||||
create_clock -period "16 MHz" -name clock_phi_d {MOS6502CpuMon:wrapper|Phi0_d}
|
||||
|
||||
# Trig(0) clock input
|
||||
create_clock -period "16 MHz" -name clock_trig0 [get_ports TRIG[0]]
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
# Doing this manually above so we can name the clock
|
||||
# derive_pll_clocks
|
||||
|
||||
#create_generated_clock -source {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]}
|
||||
|
||||
create_generated_clock -source [get_ports clock] -divide_by 25 -multiply_by 12 -duty_cycle 50.00 -name clock_avr {wrapper|inst_dcm0|altpll_component|auto_generated|pll1|clk[0]}
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
derive_clock_uncertainty
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
set_clock_groups -asynchronous -group {clock_avr} -group {clock_phi_d}
|
||||
set_clock_groups -asynchronous -group {clock_phi_d} -group {clock_avr}
|
||||
|
||||
set_clock_groups -asynchronous -group {clock_avr} -group {clock_trig0}
|
||||
set_clock_groups -asynchronous -group {clock_trig0} -group {clock_avr}
|
||||
@@ -14,6 +14,9 @@ F_CPU = 24000000
|
||||
# Note: F_CPU / 16 / BAUD need to be close to an integer
|
||||
BAUD = 115200
|
||||
|
||||
# Size of the XPM Memory in words
|
||||
XPM_SIZE = 9216
|
||||
|
||||
# Common include files
|
||||
include $(COMMON)/Makefile_$(TARGET).inc
|
||||
include $(COMMON)/Makefile_Altera.inc
|
||||
|
||||
@@ -14,6 +14,9 @@ F_CPU = 24000000
|
||||
# Note: F_CPU / 16 / BAUD need to be close to an integer
|
||||
BAUD = 115200
|
||||
|
||||
# Size of the XPM Memory in words
|
||||
XPM_SIZE = 9216
|
||||
|
||||
# Common include files
|
||||
include $(COMMON)/Makefile_$(TARGET).inc
|
||||
include $(COMMON)/Makefile_Altera.inc
|
||||
|
||||
Reference in New Issue
Block a user